Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8046726 | Waiver mechanism for physical verification of system designs | Michael Josephides, Lisa M. Miller | 2011-10-25 |
| 7853901 | Unified layer stack architecture | Thomas R. O'Brien, Richard Blinne | 2010-12-14 |
| 7829973 | N cell height decoupling circuit | Richard T. Schultz, Thomas R. O'Brien, David M. Ratchkov, Stefan G. Block | 2010-11-09 |
| 7480878 | Method and system for layout versus schematic validation of integrated circuit designs | Alan Holesovsky, Brent Wray Acott | 2009-01-20 |
| 7302654 | Method of automating place and route corrections for an integrated circuit design from physical design validation | Michael Josephides, Richard Blinne | 2007-11-27 |
| 7260803 | Incremental dummy metal insertions | Richard Blinne, Vikram Shrowty, Lena Montecillo | 2007-08-21 |
| 7231626 | Method of implementing an engineering change order in an integrated circuit design by windows | Jason Hoff, Michael Josephides, Daniel W. Prevedel, Richard Blinne, Johathan P. Kuppinger | 2007-06-12 |
| 7219317 | Method and computer program for verifying an incremental change to an integrated circuit design | Richard Blinne, Jonathan P. Kuppinger | 2007-05-15 |
| 7149989 | Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design | Alan Holesovsky, Lisa M. Miller, Jonathan P. Kuppinger | 2006-12-12 |
| 7107559 | Method of partitioning an integrated circuit design for physical design verification | Richard Blinne, Jonathan P. Kuppinger | 2006-09-12 |
| 7051318 | Web based OLA memory generator | Cristian T. Crisan, Balaji Ekambaram, Eugene Anikin | 2006-05-23 |
| 7007248 | Method and apparatus for implementing engineering change orders | Richard Blinne, Venugopalan Pranesan | 2006-02-28 |
| 6775811 | Chip design method for designing integrated circuit chips with embedded memories | Michael Josephides, Tom O'Brien, David A. Morgan | 2004-08-10 |
| 6691288 | Method to debug IKOS method | Nader Fakhry, Jayendra P. Gagvani | 2004-02-10 |
| 6668359 | Verilog to vital translator | Nader Fakhry | 2003-12-23 |
| 6658630 | Method to translate UDPs using gate primitives | Vance Threatt | 2003-12-02 |
| 6453451 | Generating standard delay format files with conditional path delay for designing integrated circuits | Kenton Dalton | 2002-09-17 |