Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7065734 | Method of generating multiple hardware description language configurations for a phase locked loop from a single generic model for integrated circuit design | — | 2006-06-20 |
| 6951017 | Design system upgrade migration | — | 2005-09-27 |
| 6496962 | Standard library generator for cell timing model | — | 2002-12-17 |
| 6453451 | Generating standard delay format files with conditional path delay for designing integrated circuits | Viswanathan Lakshmanan | 2002-09-17 |