Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9317087 | Memory column drowsy control | Ravindraraj Ramaraju, Jianan Yang, Thomas W. Liston, George P. Hoekstra, Andrew C. Russell | 2016-04-19 |
| 9263100 | Bypass system and method that mimics clock to data memory read timing | Bradley J. Garni, Huy Van Pham, Glenn E. Starnes, Thomas W. Liston | 2016-02-16 |
| 9026808 | Memory with word level power gating | Jianan Yang, Thomas W. Liston | 2015-05-05 |
| 8995178 | SRAM with embedded ROM | Jianan Yang, Brad J. Garni | 2015-03-31 |
| 8766703 | Method and apparatus for sensing on-chip characteristics | Jianan Yang, James D. Burnett, Thomas W. Liston | 2014-07-01 |
| 7746716 | Memory having a dummy bitline for timing control | Lawrence F. Childs, Olga R. Lu, Glenn E. Starnes | 2010-06-29 |
| 6675139 | Floor plan-based power bus analysis and design tool for integrated circuits | Richard A. Laubhan, Richard T. Schultz | 2004-01-06 |
| 6028995 | Method of determining delay in logic cell models | Anura P. Jayasumana | 2000-02-22 |