Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Through-silicon via layout for multi-die integrated circuits

Through-silicon via layout for multi-die integrated circuits

US Patent 12107076 · Granted Oct 1, 2024

Estimated economic value: $299,271,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic setup and hold times adjustment for memories2025
Devices and systems for flying bitline with jumper cell2025
System and method for SEU detection and correction2025
Dynamic buffer management in multi-client token flow control routers2025
Arrangement and thermal management of 3D stacked dies2025
ECC optimization2025
Sharing package pins in a multi-chip module (MCM)2024
SRAM power savings and write assist2024
Multicast in the probe channel2024
Dual read port latch array bitcell2024
Single event upset tolerant memory device2024
Split read port latch array bit cell2024