Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6557078 | Cache chain structure to implement high bandwidth low latency cache memory subsystem | Terry L Lyon, Reid James Riedlinger, Thomas Grutkowski | 2003-04-29 |
| 6539457 | Cache address conflict mechanism without store buffers | Reid James Riedlinger, Thomas Grutkowski | 2003-03-25 |
| 6507892 | L1 cache memory | Terry L Lyon, Reid James Riedlinger, Tom Grutkowski | 2003-01-14 |
| 6470374 | Carry look-ahead for bi-endian adder | Daming Jin, Tom Grutkowski | 2002-10-22 |
| 6453427 | Method and apparatus for handling data errors in a computer system | Nhon Quach, John Fu, James O. Hays, Valentin Anders, Sorin Iacobovici +1 more | 2002-09-17 |
| 6427191 | High performance fully dual-ported, pipelined cache design | John Fu, Gregory S. Mathews | 2002-07-30 |
| 6427188 | Method and system for early tag accesses for lower-level caches in parallel with first-level cache | Terry L Lyon, Eric Delano | 2002-07-30 |
| 6427189 | Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline | Reid James Riedlinger, Tom Grutkowski | 2002-07-30 |
| 6418521 | Hierarchical fully-associative-translation lookaside buffer structure | Gregory S. Mathews, John Wai Cheong Fu, Stuart E. Sailer | 2002-07-09 |
| 6408380 | Execution of an instruction to load two independently selected registers in a single cycle | Jerome C. Huck, Glenn T. Colon-Bonet, Alan H. Karp, David Allen Fotland | 2002-06-18 |
| 6381678 | Processing ordered data requests to a memory | John Fu, Gregory S. Mathews, Stuart E. Sailer, Jeng-Jye Shaw | 2002-04-30 |
| 6272597 | Dual-ported, pipelined, two level cache system | John Fu, Gregory S. Mathews, Stuart E. Sailer | 2001-08-07 |
| 6226763 | Method and apparatus for performing cache accesses | John Fu | 2001-05-01 |
| 6185660 | Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss | Sorin Iacobovici | 2001-02-06 |
| 6134636 | Method and apparatus for storing data in a memory array | Gregory S. Mathews, John Fu | 2000-10-17 |
| 6105115 | Method and apparatus for managing a memory array | Gregory S. Mathews | 2000-08-15 |
| 5870387 | Method and apparatus for initializing a ring | — | 1999-02-09 |
| 5860095 | Conflict cache having cache miscounters for a computer memory system | Sorin Iacobovici | 1999-01-12 |
| 5696939 | Apparatus and method using a semaphore buffer for semaphore instructions | Sorin Iacobovici | 1997-12-09 |
| 5664148 | Cache arrangement including coalescing buffer queue for non-cacheable data | Sorin Iacobovici | 1997-09-02 |
| 5652859 | Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues | Sorin Iacobovici | 1997-07-29 |
| 5577227 | Method for decreasing penalty resulting from a cache miss in multi-level cache system | James S. Finnell | 1996-11-19 |