Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7206921 | Micro-operation un-lamination | Zeev Sperber, Robert Valentine | 2007-04-17 |
| 6920546 | Fusion of processor micro-operations | Ittai Anati, Zeev Sperber, Robert Valentine | 2005-07-19 |
| 5964868 | Method and apparatus for implementing a speculative return stack buffer | Nicolas Kacevas, Farah Jubran | 1999-10-12 |
| 5928352 | Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry | Jacob Doweck | 1999-07-27 |
| 5860147 | Method and apparatus for replacement of entries in a translation look-aside buffer | Jacob Doweck | 1999-01-12 |
| 5842008 | Method and apparatus for implementing a branch target buffer cache with multiple BTB banks | Nicolas Kacevas | 1998-11-24 |
| 5764932 | Method and apparatus for implementing a dual processing protocol between processors | Gil Stoler | 1998-06-09 |
| 5379396 | Write ordering for microprocessor depending on cache hit and write buffer content | Itamar Kazachinsky, Michael Kagan | 1995-01-03 |
| 5367660 | Line buffer for cache memory | Tal Gat, Michael Kagan | 1994-11-22 |
| 5301298 | Processor for multiple cache coherent protocols | Michael Kagan, Itamar Kazachinsky, Tal Gat | 1994-04-05 |