Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry

Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry

US Patent 5928352 · Granted Jul 27, 1999

Estimated economic value: $181,024,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatuses, methods, and systems for hashing instructions2025
Restricting usage of encryption keys by untrusted software2024
Apparatuses, methods, and systems for hashing instructions2023
Apparatuses, methods, and systems for hashing instructions2023
Co-existence of trust domain architecture with multi-key total memory encryption2022
Apparatuses, methods, and systems for hashing instructions2021
Restricting usage of encryption keys by untrusted software2021
Linear to physical address translation with support for page attributes2021
Apparatuses, methods, and systems for hashing instructions2020
Linear to physical address translation with support for page attributes2015
Linear to physical address translation with support for page attributes2015
Method and apparatus for memory encryption with integrity check and protection a2015