Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11023998 | Apparatus and method for shared resource partitioning through credit management | Niranjan L. Cooray, Madhura Joshi, Satyanarayana Nekkalapu | 2021-06-01 |
| 10552937 | Scalable memory interface for graphical processor unit | Niranjan L. Cooray, Altug Koker, Parth Damani, Satyanarayana Nekkalapu | 2020-02-04 |
| 10372621 | Mechanism to support variable size page translations | Niranjan L. Cooray, Altug Koker, Parth Damani, David I. Standring | 2019-08-06 |
| 10249017 | Apparatus and method for shared resource partitioning through credit management | Niranjan L. Cooray, Madhura Joshi, Satyanarayana Nekkalapu | 2019-04-02 |
| 7260706 | Branch misprediction recovery using a side memory | — | 2007-08-21 |
| 7174444 | Preventing a read of a next sequential chunk in branch prediction of a subject chunk | Eran Altshuler, Oded Lempel, Robert Valentine | 2007-02-06 |
| 7058795 | Method and apparatus of branch prediction | Eran Altshuler | 2006-06-06 |
| 7047400 | Single array banked branch target buffer | — | 2006-05-16 |
| 6757815 | Single array banked branch target buffer | — | 2004-06-29 |
| 6643770 | Branch misprediction recovery using a side memory | — | 2003-11-04 |
| 6601161 | Method and system for branch target prediction using path information | Lihu Rappoport, Ronny Ronen, Oded Lempel | 2003-07-29 |
| 6429873 | Addressing of monolithic texture maps | Val G. Cook, Peter L. Doyle | 2002-08-06 |
| 6397297 | Dual cache with multiple interconnection operation modes | Zeev Sperber, Jack Doweck, Roy Nesher | 2002-05-28 |
| 5964868 | Method and apparatus for implementing a speculative return stack buffer | Simcha Gochman, Farah Jubran | 1999-10-12 |
| 5842008 | Method and apparatus for implementing a branch target buffer cache with multiple BTB banks | Simcha Gochman | 1998-11-24 |