Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10746792 | Debug mechanisms for a processor circuit | Ron Diamant, Nafea Bshara | 2020-08-18 |
| 10691576 | Multiple reset types in a system | Yaniv Shapira, Adi Habusha | 2020-06-23 |
| 10635589 | System and method for managing transactions | Adi Habusha, Said Bshara, Nafea Bshara | 2020-04-28 |
| 10489546 | Modular system on chip configuration system | — | 2019-11-26 |
| 10185678 | Universal offloading engine | Erez Izenberg | 2019-01-22 |
| 10078568 | Debugging a computing device | Yaniv Shapira | 2018-09-18 |
| 10061700 | System and method for managing transactions | Adi Habusha, Said Bshara, Nafea Bshara | 2018-08-28 |
| 10044456 | Clock generation with non-integer clock dividing ratio | Yaniv Shapira | 2018-08-07 |
| 10019546 | Modular system on chip configuration system | — | 2018-07-10 |
| RE46766 | Cache pre-fetch architecture and method | Tarek Rohana, Adi Habusha | 2018-03-27 |
| 9800400 | Clock phase alignment in data transmission | — | 2017-10-24 |
| 9628211 | Clock generation with non-integer clock dividing ratio | Yaniv Shapira | 2017-04-18 |
| 9411731 | System and method for managing transactions | Adi Habusha, Said Bshara, Nafea Bshara | 2016-08-09 |
| 9141546 | System and method for managing transactions | Adi Habusha, Said Bshara, Nafea Bshara | 2015-09-22 |
| 8954681 | Multi-stage command processing pipeline and method for shared cache access | Tarek Rohana | 2015-02-10 |
| 8938585 | Transparent processing core and L2 cache connection | Tarek Rohana | 2015-01-20 |
| 8760324 | Synchronous multi-clock protocol converter | Eitan Joshua, Shaul Chapman | 2014-06-24 |
| 8688911 | Transparent processing core and L2 cache connection | Tarek Rohana | 2014-04-01 |
| 8499123 | Multi-stage pipeline for cache access | Tarek Rohana | 2013-07-30 |
| 8484421 | Cache pre-fetch architecture and method | Tarek Rohana, Adi Habusha | 2013-07-09 |
| 8332590 | Multi-stage command processing pipeline and method for shared cache access | Tarek Rohana | 2012-12-11 |
| 8117395 | Multi-stage pipeline for cache access | Tarek Rohana | 2012-02-14 |
| 8089378 | Synchronous multi-clock protocol converter | Eitan Joshua, Shaul Chapman | 2012-01-03 |
| 7932768 | Apparatus and method for generating a clock signal | Ido Bourstein, Yiftach Banai | 2011-04-26 |
| 7652516 | Apparatus and method for generating a clock signal | Ido Bourstein, Yiftach Banai | 2010-01-26 |