Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for reducing clock frequency during low workload periods

Method and apparatus for reducing clock frequency during low workload periods

US Patent 7721129 · Granted May 18, 2010

Estimated economic value: $11,091,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Compressed instruction format2021
In-lane vector shuffle instructions2020
Processor core power event tracing2020
In-lane vector shuffle instructions2019
In-lane vector shuffle instructions2019
In-lane vector shuffle instructions2019
In-lane vector shuffle instructions2019
Compressed instruction format2018
Processor core power event tracing2018
Real time instruction trace processors, methods, and systems2017
Vector shuffle instructions operating on multiple lanes each having a plurality 2017
Providing status of a processing device with periodic synchronization point in i2017