Issued Patents All Time
Showing 26–50 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7009437 | Smart buffer circuit to match a delay over a range of loads | Javed S. Barkatullah | 2006-03-07 |
| 6928572 | Multistage clock delay circuit and method | Giao N. Pham | 2005-08-09 |
| 6828838 | Vectored flip-flops and latches with embedded output-merge logic and shared clock drivers | Kumar Anshumali | 2004-12-07 |
| 6750689 | Method and apparatus for correcting a clock duty cycle in a clock distribution network | Javed S. Barkatullah | 2004-06-15 |
| 6732136 | Differential, low voltage swing reducer | Feng Chen, Shahram Jamshidi | 2004-05-04 |
| 6667645 | Pulsed clock signal transfer circuits with dynamic latching | Eitan Rosen | 2003-12-23 |
| 6629255 | Generating a 2-phase clock using a non-50% divider circuit | Javed S. Barkatullah | 2003-09-30 |
| 6611920 | Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit | Javed S. Barkatullah, Douglas M. Carmean | 2003-08-26 |
| 6580294 | Zipper domino carry generate cell for fast adders | — | 2003-06-17 |
| 6573755 | Symmetric differential domino “AND gate” | Giao N. Pham, Paul D. Madland | 2003-06-03 |
| 6573772 | Method and apparatus for locking self-timed pulsed clock | Xia Dai | 2003-06-03 |
| 6567836 | Multi-level carry-skip adder | — | 2003-05-20 |
| 6531897 | Global clock self-timed circuit with self-terminating precharge for high frequency applications | Mark S. Milshtein, Milo D. Sprague, Terry I. Chappell | 2003-03-11 |
| 6529635 | Shape-based image compression/decompression using pattern matching | Susan Julia Corwin | 2003-03-04 |
| 6487675 | Processor having execution core sections operating at different clock rates | David J. Sager, Glenn J. Hinton, Michael D. Upton | 2002-11-26 |
| 6448818 | Apparatus, method and system for a ratioed NOR logic arrangement | — | 2002-09-10 |
| 6442089 | Multi-level, low voltage swing sensing scheme for high speed memory design | Kevin X. Zhang | 2002-08-27 |
| 6392466 | Apparatus, method and system for a controllable pulse clock delay arrangement to control functional race margins in a logic data path | — | 2002-05-21 |
| 6385631 | Priority encoder | Feng Chen | 2002-05-07 |
| 6346828 | Method and apparatus for pulsed clock tri-state control | Eitan Rosen | 2002-02-12 |
| 6331793 | Apparatus, method and system for pulse passgate topologies | Xia Dai | 2001-12-18 |
| 6329857 | Apparatus, method and system for a logic arrangement having mutually exclusive outputs controlled by buffering cross-coupled devices | — | 2001-12-11 |
| 6323698 | Apparatus, method and system for providing LVS enables together with LVS data | — | 2001-11-27 |
| 6292401 | Method and apparatus for global bitline multiplexing for a high-speed memory | Kevin X. Zhang | 2001-09-18 |
| 6256745 | Processor having execution core sections operating at different clock rates | David J. Sager, Glenn J. Hinton, Michael D. Upton | 2001-07-03 |