Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6018786 | Trace based instruction caching | Robert F. Krick, Glenn J. Hinton, Michael D. Upton, Chan Woo Lee | 2000-01-25 |
| 5966544 | Data speculatable processor having reply architecture | — | 1999-10-12 |
| 5835745 | Hardware instruction scheduler for short execution unit latencies | James B. Saxe | 1998-11-10 |
| 5828868 | Processor having execution core sections operating at different clock rates | Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton | 1998-10-27 |
| 5828874 | Past-history filtered branch prediction | Simon C. Steely, Jr. | 1998-10-27 |
| 5812810 | Instruction coding to support parallel execution of programs | — | 1998-09-22 |
| 5717883 | Method and apparatus for parallel execution of computer programs using information providing for reconstruction of a logical sequential program | — | 1998-02-10 |
| 5680644 | Low delay means of communicating between systems on different clocks | — | 1997-10-21 |
| 5619662 | Memory reference tagging | Simon C. Steely, Jr., David B. Fite, Jr. | 1997-04-08 |
| 5581719 | Multiple block line prediction | Simon C. Steely, Jr. | 1996-12-03 |
| 5564118 | Past-history filtered branch prediction | Simon C. Steely, Jr., William B. Noyce | 1996-10-08 |
| 5519841 | Multi instruction register mapper | Simon C. Steely, Jr., David B. Fite, Jr. | 1996-05-21 |
| 5428807 | Method and apparatus for propagating exception conditions of a computer system | Francis X. McKeen, Michael C. Adler, Joel S. Emer, Robert P. Nix, P. Geoffrey Lowny | 1995-06-27 |
| 5421022 | Apparatus and method for speculatively executing instructions in a computer system | Francis X. McKeen, Michael C. Adler, Joel S. Emer, Robert P. Nix, P. Geoffrey Lowney | 1995-05-30 |
| 5420990 | Mechanism for enforcing the correct order of instruction execution | Francis X. McKeen, Michael C. Adler, Joel S. Emer, Robert P. Nix, P. Geoffrey Lowney | 1995-05-30 |
| 5359630 | Method and apparatus for realignment of synchronous data | Paul Wade, Andrey Varpahovsky | 1994-10-25 |
| 5283873 | Next line prediction apparatus for a pipelined computed system | Simon C. Steely, Jr. | 1994-02-01 |
| 5197132 | Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery | Simon C. Steely, Jr. | 1993-03-23 |
| 5179673 | Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline | Simon C. Steely, Jr. | 1993-01-12 |
| 5003459 | Cache memory system | Raj K. Ramanujan, Simon C. Steely, Jr., Peter J. Bannon | 1991-03-26 |
| 5003537 | Method of transmitting data at full bandwidth within a synchronous system when clock skew plus delay exceeds the cycle time | — | 1991-03-26 |
| 4979190 | Method and apparatus for stabilized data transmission | Leon D. Hesch, Andrew D. Ingraham, William A. Samaras | 1990-12-18 |
| 4881165 | Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems | Anne S. Valiton, Jay C. Stickney, Raj K. Ramanujan | 1989-11-14 |
| 4825412 | Lockout registers | Raj K. Ramanujan, Jeffrey L. Bell | 1989-04-25 |
| 4811364 | Method and apparatus for stabilized data transmission | Leon D. Hesch, Andrew D. Ingraham, William A. Samaras | 1989-03-07 |