Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6877086 | Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter | Darrell D. Boggs, Douglas M. Carmean, Per Hammarlund, Francis X. McKeen, Ronak Singhal | 2005-04-05 |
| 6792446 | Storing of instructions relating to a stalled thread | Amit Merchant, Darrell Buggs | 2004-09-14 |
| 6785803 | Processor including replay queue to break livelocks | Amit Merchant, James D. Allen, IV | 2004-08-31 |
| 6735688 | Processor having replay architecture with fast and slow replay paths | Michael D. Upton, Darrell D. Boggs, Glenn J. Hinton | 2004-05-11 |
| 6735682 | Apparatus and method for address calculation | Ross Segelken, Feng Chen | 2004-05-11 |
| 6704861 | Mechanism for executing computer instructions in parallel | Francis X. McKeen, Michael C. Adler, Joel S. Emer, Robert P. Nix, P. Geoffrey Lowney | 2004-03-09 |
| 6665792 | Interface to a memory system for a processor having a replay system | Amit Merchant, Darrell D. Boggs | 2003-12-16 |
| 6636976 | Mechanism to control di/dt for a microprocessor | Edward T. Grochowski, Vivek Tiwari, Ian A. Young, David J. Ayers | 2003-10-21 |
| 6633970 | Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer | David W. Clift, Darrell D. Boggs | 2003-10-14 |
| 6631454 | Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies | — | 2003-10-07 |
| 6542921 | Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor | — | 2003-04-01 |
| 6487675 | Processor having execution core sections operating at different clock rates | Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton | 2002-11-26 |
| 6425055 | Way-predicting cache memory | Glenn J. Hinton | 2002-07-23 |
| 6385715 | Multi-threading for a processor utilizing a replay queue | Amit Merchant, Darrell D. Boggs | 2002-05-07 |
| 6341327 | Content addressable memory addressable by redundant form input | — | 2002-01-22 |
| 6334182 | Scheduling operations using a dependency matrix | Amit Merchant | 2001-12-25 |
| 6304953 | Computer processor with instruction-specific schedulers | Alexander P. Henstrom | 2001-10-16 |
| 6282629 | Pipelined processor for performing parallel instruction recording and register assigning | — | 2001-08-28 |
| 6256745 | Processor having execution core sections operating at different clock rates | Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton | 2001-07-03 |
| 6216234 | Processor having execution core sections operating at different clock rates | Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton | 2001-04-10 |
| 6212626 | Computer processor having a checker | Amit Merchant | 2001-04-03 |
| 6172933 | Redundant form address decoder for memory system | — | 2001-01-09 |
| 6170038 | Trace based instruction caching | Robert F. Krick, Glenn J. Hinton, Michael D. Upton, Chan Woo Lee | 2001-01-02 |
| 6163838 | Computer processor with a replay system | Amit Merchant, Darrell D. Boggs | 2000-12-19 |
| 6094717 | Computer processor with a replay system having a plurality of checkers | Amit Merchant, Darrell D. Boggs, Michael D. Upton | 2000-07-25 |