Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12282658 | System and method for large memory transaction (LMT) stores | Aadeetya Shreedhar, Jason D. Zebchuk, Wilson P. Snyder, II, Joseph Featherston | 2025-04-22 |
| 12032488 | Circuit and method for translation lookaside buffer (TLB) implementation | Oded Tsur | 2024-07-09 |
| 11960727 | System and method for large memory transaction (LMT) stores | Aadeetya Shreedhar, Jason D. Zebchuk, Wilson P. Snyder, II, Joseph Featherston | 2024-04-16 |
| 11620225 | System and method for mapping memory addresses to locations in set-associative caches | — | 2023-04-04 |
| 11474953 | Configuration cache for the ARM SMMUv3 | Manan Salvi | 2022-10-18 |
| 11416405 | System and method for mapping memory addresses to locations in set-associative caches | — | 2022-08-16 |
| 10339054 | Instruction ordering for in-progress operations | Shubhendu Sekhar Mukherjee, Mike Bertone | 2019-07-02 |
| 10303514 | Sharing resources in a multi-context computing system | Wilson P. Snyder, II, Varada Ogale, Anna Kujtkowski | 2019-05-28 |
| 10078601 | Approach for interfacing a pipeline with two or more interfaces in a processor | Wilson P. Snyder, II, Anna Kujtkowski, Paul G. Scrobohaci | 2018-09-18 |
| 9910776 | Instruction ordering for in-progress operations | Shubhendu Sekhar Mukherjee, Mike Bertone | 2018-03-06 |
| 9678717 | Distributing resource requests in a computing system | Wilson P. Snyder, II, Varada Ogale, Anna Kujtkowski | 2017-06-13 |
| 9405702 | Caching TLB translations using a unified page table walker cache | Shubhendu Sekhar Mukherjee, Mike Bertone | 2016-08-02 |