| 11880260 |
Instruction subset implementation for low power operation |
Edward J. McLellan |
2024-01-23 |
| 11586472 |
Method of task transition between heterogenous processors |
Alexander J. Branover, Benjamin Tsien |
2023-02-21 |
| 11347650 |
Word type/boundary propagation with memory performance applications |
David A. Roberts |
2022-05-31 |
| 11216250 |
Dynamic, variable bit-width numerical precision on field-programmable gate arrays for machine learning tasks |
Nicholas Malaya |
2022-01-04 |
| 10698472 |
Instruction subset implementation for low power operation |
Edward J. McLellan |
2020-06-30 |
| 10452548 |
Preemptive cache writeback with transaction support |
David A. Roberts |
2019-10-22 |
| 10289413 |
Hybrid analog-digital floating point number representation and arithmetic |
David A. Roberts, David John Cownie |
2019-05-14 |
| 10209991 |
Instruction set and micro-architecture supporting asynchronous memory access |
Meenakshi Sundaram Bhaskaran, David A. Roberts, Anthony Asaro, Amin Farmahini-Farahani |
2019-02-19 |
| 10164639 |
Virtual FPGA management and optimization system |
David A. Roberts, Andrew G. Kegel |
2018-12-25 |
| 9851945 |
Bit remapping mechanism to enhance lossy compression in floating-point applications |
Nam-Duong Duong, Dongping Zhang |
2017-12-26 |
| 9262303 |
Automated semiconductor design flaw detection system |
Christopher A. Schalick, Roderick B. Sullivan, II, Matthew D. Kopser |
2016-02-16 |
| 7792933 |
System and method for performing design verification |
Michael Butts |
2010-09-07 |
| 4888691 |
Method for disk I/O transfer |
Paul L. George, David M. Waxman, Randall T. Sybel, Kevin O'Brien, Joseph M. Spatara |
1989-12-19 |