Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

US Patent 7565513 · Granted Jul 21, 2009

Estimated economic value: $9,005,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Segmented non-contiguous reverse map table2025
Method and apparatus for deskewing die to die communication between system on ch2025
Method for reducing hydrogen sulfide (H2S) content of H2S-containing subterranea2025
Method for reducing hydrogen sulfide in a subterranean formation2025
Process for removing hydrogen sulfide from a gas composition2024
Weighted drilling fluid composition2024
Processor-guided execution of offloaded instructions using fixed function operat2024
Drilling fluid composition and method for removing hydrogen sulfide content usin2024
Processor-guided execution of offloaded instructions using fixed function operat2024
Hypervisor secure event handling at a processor2023
Behavior-driven die management on solid-state drives2023
Executing a set of load operations for a gather-load instruction and controlling2022