Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11038526 | Energy efficient adaptive data encoding method and circuit | Greg Sadowski | 2021-06-15 |
| 11023242 | Method and apparatus for asynchronous scheduling | Greg Sadowski, Syed Gilani | 2021-06-01 |
| 11016763 | Implementing a micro-operation cache with compaction | Jagadish B. Kotra | 2021-05-25 |
| 10990393 | Address-based filtering for load/store speculation | Krishnan V. Ramani, Susumu Mashimo | 2021-04-27 |
| 10983915 | Flexible dictionary sharing for compressed caches | Alexander D. Breslow | 2021-04-20 |
| 10908991 | Bit error protection in cache memories | Shrikanth Ganapathy | 2021-02-02 |
| 10884751 | Method and apparatus for virtualizing the micro-op cache | Jagadish B. Kotra | 2021-01-05 |
| 10884940 | Method and apparatus for using compression to improve performance of low voltage caches | Shrikanth Ganapathy, Shomit N. Das, Matthew Tomei | 2021-01-05 |
| 10860418 | System and method for protecting GPU memory instructions against faults | Michael Mantor, Sudhanva Gurumurthi | 2020-12-08 |
| 10853075 | Controlling accesses to a branch prediction unit for sequences of fetch groups | Varun Agrawal, Adithya Yalavarti, Jingjie Qian | 2020-12-01 |
| 10749545 | Compressing tags in software and hardware semi-sorted caches | Alexander D. Breslow, Nuwan Jayasena | 2020-08-18 |
| 10698692 | Controlling the operating speed of stages of an asynchronous pipeline | Greg Sadowski, Shomit N. Das | 2020-06-30 |
| 10671535 | Stride prefetching across memory pages | Paul Keltcher, Marius Evers, Chitresh Narasimhaiah | 2020-06-02 |
| 10566996 | Energy efficient adaptive data encoding method and circuit | Greg Sadowski | 2020-02-18 |
| 10558606 | Reliable voltage scaled links for compressed data | Shomit N. Das, Matthew Tomei, Shrikanth Ganapathy | 2020-02-11 |
| 10379944 | Bit error protection in cache memories | Shrikanth Ganapathy, Steven Raasch | 2019-08-13 |
| 10255132 | System and method for protecting GPU memory instructions against faults | Michael Mantor, Sudhanva Gurumurthi | 2019-04-09 |
| 9928191 | Communication device with selective encoding | Greg Sadowski | 2018-03-27 |
| 9529720 | Variable distance bypass between tag array and data array pipelines in a cache | Marius Evers, Carl Dietz, Richard E. Klass, Ravindra N. Bhargava | 2016-12-27 |
| 9424195 | Dynamic remapping of cache lines | Johnsy Kanjirapallil John, Phillip E. Nevius, Robert G. Gelinas | 2016-08-23 |
| 9304919 | Detecting multiple stride sequences for prefetching | Paul Keltcher | 2016-04-05 |
| 9223705 | Cache access arbitration for prefetch requests | Ramkumar Jayaseelan | 2015-12-29 |
| 9189326 | Detecting and correcting hard errors in a memory array | Johnsy Kanjirapallil John, Robert G. Gelinas, Vilas Sridharan, Phillip E. Nevius | 2015-11-17 |
| 9058277 | Dynamic evaluation and reconfiguration of a data prefetcher | Sharad Dilip Bade, Alok Garg, Paul Keltcher, Marius Evers, Chitresh Narasimhaiah | 2015-06-16 |
| 9058278 | Tracking prefetcher accuracy and coverage | Paul Keltcher | 2015-06-16 |