Issued Patents All Time
Showing 25 most recent of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406426 | Hybrid render with deferred primitive batch binning | Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi +4 more | 2025-09-02 |
| 12361628 | Configurable multiple-die graphics processing unit | Mark Fowler, Samuel D. Naffziger, Mark Leather | 2025-07-15 |
| 12327124 | Vertical and horizontal broadcast of shared operands | Sateesh Lagudu, Allen H. Rush, Arun Vaidyanathan Ananthanarayan, Prasad Nagabhushanamgari, Maxim V. Kazakov | 2025-06-10 |
| 12299413 | Dual vector arithmetic logic unit | Bin He, Brian D. Emberling, Mark Leather | 2025-05-13 |
| 12254527 | Reconfigurable virtual graphics and compute processor pipeline | Timour Paltashev, Rex Eldon McCrary | 2025-03-18 |
| 12229570 | Block data load with transpose into memory | Bin He, Brian D. Emberling, Liang Huang, Chao Liu | 2025-02-18 |
| 12217021 | Processing unit with small footprint arithmetic logic unit | Bin He, Shubh Shah | 2025-02-04 |
| 12205218 | Spatial partitioning in a multi-tenancy graphics processing unit | Mark Leather | 2025-01-21 |
| 12169896 | Graphics primitives and positions through memory buffers | Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey, Christopher J. Brennan +2 more | 2024-12-17 |
| 12153958 | VMID as a GPU task container for virtualization | Anirudh R. Acharya, Rex Eldon McCrary, Anthony Asaro, Jeffrey G. Cheng, Mark Fowler | 2024-11-26 |
| 12153957 | Hierarchical work scheduling | Matthaeus G. Chajdas, Christopher J. Brennan, Robert W. Martin, Nicolai Haehnle | 2024-11-26 |
| 12067401 | Stream processor with low power parallel matrix multiply pipeline | Jiasheng Chen, Yunxiao Zou, Allen H. Rush | 2024-08-20 |
| 12032487 | Access log and address translation log for a processor | Benjamin T. Sander, Mark Fowler, Anthony Asaro, Gongxian Jeffrey Cheng | 2024-07-09 |
| 11995149 | Sparse matrix-vector multiplication | Sateesh Lagudu, Allen H. Rush | 2024-05-28 |
| 11954036 | Prefetch kernels on data-parallel processors | Nuwan Jayasena, James M. O'Connor | 2024-04-09 |
| 11954782 | Hybrid render with preferred primitive batch binning and sorting | Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio | 2024-04-09 |
| 11948223 | Redundancy method and apparatus for shader column repair | Jeffrey T. Brady, Angel E. Socarras | 2024-04-02 |
| 11880683 | Packed 16 bits instruction pipeline | Jiasheng Chen, Bin He, Yunxiao Zou, Radhakrishna Giduthuri, Eric J. Finger +1 more | 2024-01-23 |
| 11880926 | Hybrid render with deferred primitive batch binning | Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi +4 more | 2024-01-23 |
| 11854139 | Graphics processing unit traversal engine | Konstantin I. Shkurko | 2023-12-26 |
| 11830817 | Creating interconnects between dies using a cross-over die and through-die vias | Rahul Agarwal, Raja Swaminathan, Michael Alfano, Gabriel H. Loh, Alan D. Smith +1 more | 2023-11-28 |
| 11803385 | Broadcast synchronization for dynamically adaptable arrays | Sateesh Lagudu, Arun Vaidyanathan Ananthanarayan, Allen H. Rush | 2023-10-31 |
| 11768664 | Processing unit with mixed precision operations | Bin He, Jiasheng Chen | 2023-09-26 |
| 11762658 | Matrix multiplication unit with flexible precision operations | Bin He, Jiasheng Chen, Jian Huang | 2023-09-19 |
| 11726868 | System and method for protecting GPU memory instructions against faults | John Kalamatianos, Sudhanva Gurumurthi | 2023-08-15 |