Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11720328 | Processing unit with small footprint arithmetic logic unit | Bin He, Shubh Shah | 2023-08-08 |
| 11675568 | Dual vector arithmetic logic unit | Bin He, Brian D. Emberling, Mark Leather | 2023-06-13 |
| 11635967 | Vertical and horizontal broadcast of shared operands | Sateesh Lagudu, Allen H. Rush, Arun Vaidyanathan Ananthanarayan, Prasad Nagabhushanamgari, Maxim V. Kazakov | 2023-04-25 |
| 11630667 | Dedicated vector sub-processor system | Jiasheng Chen, Bin He, Jian Huang | 2023-04-18 |
| 11625807 | Low power and low latency GPU coprocessor for persistent computing | Jiasheng Chen, Timour Paltashev, Alexander Lyashevsky, Carl K. Wakeland | 2023-04-11 |
| 11609791 | Precise suspend and resume of workloads in a processing unit | Anirudh R. Acharya | 2023-03-21 |
| 11500778 | Prefetch kernels on data-parallel processors | Nuwan Jayasena, James M. O'Connor | 2022-11-15 |
| 11494192 | Pipeline including separate hardware data paths for different instruction types | Jiasheng Chen, Yunxiao Zou, Bin He, Angel E. Socarras, QingCheng Wang +1 more | 2022-11-08 |
| 11467870 | VMID as a GPU task container for virtualization | Anirudh R. Acharya, Rex Eldon McCrary, Anthony Asaro, Jeffrey G. Cheng, Mark Fowler | 2022-10-11 |
| 11409840 | Dynamically adaptable arrays for vector and matrix operations | Sateesh Lagudu, Allen H. Rush, Arun Vaidyanathan Ananthanarayan, Prasad Nagabhushanamgari | 2022-08-09 |
| 11409536 | Pairing SIMD lanes to perform double precision operations | Bin He, Yunxiao Zou, Jiasheng Chen | 2022-08-09 |
| 11397578 | Selectively dispatching waves based on accumulators holding behavioral characteristics of waves currently executing | Randy Wayne Ramsey, William D. Isenberg | 2022-07-26 |
| 11386518 | Exception handler for sampling draw dispatch identifiers | Alexander Fuad Ashkar, Randy Wayne Ramsey, Mangesh P. Nijasure, Brian D. Emberling | 2022-07-12 |
| 11386520 | Redundancy method and apparatus for shader column repair | Jeffrey T. Brady, Angel E. Socarras | 2022-07-12 |
| 11379941 | Primitive shader | Todd Martin, Mangesh P. Nijasure, Randy Wayne Ramsey, Laurent Lefebvre | 2022-07-05 |
| 11335052 | Hybrid render with deferred primitive batch binning | Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi +4 more | 2022-05-17 |
| 11295507 | Spatial partitioning in a multi-tenancy graphics processing unit | Mark Leather | 2022-04-05 |
| 11263044 | Workload-based clock adjustment at a processing unit | Mangesh P. Nijasure, Ashkan Hosseinzadeh Namin, Louis Regniere | 2022-03-01 |
| 11226819 | Selective prefetching in multithreaded processing units | Brian D. Emberling | 2022-01-18 |
| 11200060 | Broadcast synchronization for dynamically adaptable arrays | Sateesh Lagudu, Arun Vaidyanathan Ananthanarayan, Allen H. Rush | 2021-12-14 |
| 11169811 | Graphics context bouncing | Rex Eldon McCrary, Yi Luo, Harry J. Wise, Alexander Fuad Ashkar | 2021-11-09 |
| 10970081 | Stream processor with decoupled crossbar for cross lane operations | Jiasheng Chen, Bin He, Mohammad Reza Hakami, Timothy Paul Lottes, Justin David Smith +1 more | 2021-04-06 |
| 10957094 | Hybrid render with preferred primitive batch binning and sorting | Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio | 2021-03-23 |
| 10943389 | Removing or identifying overlapping fragments after z-culling | Laurent Lefebvre, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio +4 more | 2021-03-09 |
| 10929944 | Low power and low latency GPU coprocessor for persistent computing | Jiasheng Chen, Timour Paltashev, Alexander Lyashevsky, Carl K. Wakeland | 2021-02-23 |