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Routing scheme for heterogeneous interconnected-chip networks using distributed shared memory |
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Systems and methods for multi-branch routing for interconnected chip networks |
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Pipeline including separate hardware data paths for different instruction types |
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Data reuse method based on convolutional neural network accelerator |
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Pairing SIMD lanes to perform double precision operations |
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Hybrid matrix multiplication pipeline |
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Pipeline including separate hardware data paths for different instruction types |
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Method and processing apparatus for gating redundant threads |
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