Issued Patents All Time
Showing 26–50 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11736119 | Semi-sorting compression with encoding and decoding tables | Alexander D. Breslow, Nuwan Jayasena | 2023-08-22 |
| 11726868 | System and method for protecting GPU memory instructions against faults | Michael Mantor, Sudhanva Gurumurthi | 2023-08-15 |
| 11726783 | Filtering micro-operations for a micro-operation cache in a processor | Marko Scrbak, Mahzabeen Islam, Jagadish B. Kotra | 2023-08-15 |
| 11726917 | Method and apparatus for a page-local delta-based prefetcher | Susumu Mashimo | 2023-08-15 |
| 11714652 | Zero operand instruction conversion for accelerating sparse computations in a central processing unit pipeline | Ganesh Suryanarayan Dasika | 2023-08-01 |
| 11656945 | Method and apparatus to support instruction replay for executing idempotent code in dependent processing in memory devices | Nuwan Jayasena, Sudhanva Gurumurthi, Shaizeen Aga, Shrikanth Ganapathy | 2023-05-23 |
| 11658681 | Energy efficient adaptive data encoding method and circuit | Greg Sadowski | 2023-05-23 |
| 11645073 | Address-based filtering for load/store speculation | Krishnan V. Ramani, Susumu Mashimo | 2023-05-09 |
| 11625249 | Preserving memory ordering between offloaded instructions and non-offloaded instructions | Jagadish B. Kotra | 2023-04-11 |
| 11586441 | Method and apparatus for virtualizing the micro-op cache | Jagadish B. Kotra | 2023-02-21 |
| 11586555 | Flexible dictionary sharing for compressed caches | Alexander D. Breslow | 2023-02-21 |
| 11556162 | Per-instruction energy debugging using instruction sampling hardware | Shijia Wei, Joseph L. Greathouse | 2023-01-17 |
| 11550588 | Branch target filtering based on memory region access count | Adithya Yalavarti, Varun Agrawal, Subhankar Pal, Vinesh Srinivasan | 2023-01-10 |
| 11513802 | Compressing micro-operations in scheduler entries in a processor | Michael W. Boyer, Pritam Majumder | 2022-11-29 |
| 11513801 | Controlling accesses to a branch prediction unit for sequences of fetch groups | Adithya Yalavarti, Matthew R. Poremba | 2022-11-29 |
| 11509333 | Masked fault detection for reliable low voltage cache operation | Shrikanth Ganapathy | 2022-11-22 |
| 11487671 | GPU cache management based on locality type detection | Xianwei Zhang, Bradford M. Beckmann | 2022-11-01 |
| 11481331 | Promoting prefetched data from a cache memory to registers in a processor | Jagadish B. Kotra | 2022-10-25 |
| 11455252 | Multi-class multi-label classification using clustered singular decision trees for hardware adaptation | Paul Keltcher, Mayank Chhablani, Alok Garg, Furkan Eris | 2022-09-27 |
| 11442727 | Controlling prediction functional blocks used by a branch predictor in a processor | Varun Agrawal | 2022-09-13 |
| 11409608 | Providing host-based error detection capabilities in a remote execution device | Shrikanth Ganapathy, Ross V. La Fetra, Sudhanva Gurumurthi, Shaizeen Aga, Vilas Sridharan +2 more | 2022-08-09 |
| 11397691 | Latency hiding for caches | Apostolos Kokolis, Shrikanth Ganapathy | 2022-07-26 |
| 11309911 | Semi-sorting compression with encoding and decoding tables | Alexander D. Breslow, Nuwan Jayasena | 2022-04-19 |
| 11243884 | Control flow guided lock address prefetch and filtering | Susumu Mashimo | 2022-02-08 |
| 11113065 | Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers | Susumu Mashimo, Krishnan V. Ramani, Scott Thomas Bingham | 2021-09-07 |