| 12271597 |
Memory organization for multi-mode support |
Xuan Chen, Michael John Litt |
2025-04-08 |
| 11734114 |
Programmable error correction code encoding and decoding logic |
— |
2023-08-22 |
| 11409608 |
Providing host-based error detection capabilities in a remote execution device |
Shrikanth Ganapathy, John Kalamatianos, Sudhanva Gurumurthi, Shaizeen Aga, Vilas Sridharan +2 more |
2022-08-09 |
| 11372720 |
Systems and methods for encoding metadata |
— |
2022-06-28 |
| 9354970 |
Method and apparatus for encoding erroneous data in an error correction code protected memory |
Vilas Sridharan, Vydhyanathan Kalyanasundharam, Dean A. Liberty, Amit P. Apte |
2016-05-31 |
| 8589670 |
Adjusting system configuration for increased reliability based on margin |
— |
2013-11-19 |
| 7421525 |
System including a host connected to a plurality of memory modules via a serial memory interconnect |
R. Stephen Polzin, Frederick Daniel Weber, Gerald R. Talbot, Larry D. Hewitt, Richard W. Reeves +4 more |
2008-09-02 |
| 7271613 |
Method and apparatus for sharing an input/output terminal by multiple compensation circuits |
Rohit Kumar, Sai V. Vishwanthaiah |
2007-09-18 |
| 7076686 |
Hot swapping memory method and system |
— |
2006-07-11 |
| 7016213 |
Method for initializing a system including a host and plurality of memory modules connected via a serial memory interconnect |
Richard W. Reeves, Paul C. Miranda |
2006-03-21 |
| 6990539 |
Apparatus and method of implementing BREQ routing to allow functionality with 2 way or 4 way processors |
Peter M. Arnold |
2006-01-24 |
| 5509119 |
Fast comparison method and apparatus for error corrected cache tags |
— |
1996-04-16 |
| 5155828 |
Computing system with a cache memory and an additional look-aside cache memory |
John F. Shelton |
1992-10-13 |
| 5029133 |
VLSI chip having improved test access |
Lee Fleming |
1991-07-02 |