Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12253936 | Validating inter-partition communication in microservice decomposition | Rachel Tzoref-Brill, Saurabh Sinha, Maja Vukovic | 2025-03-18 |
| 11157293 | Dynamic incident console interfaces | Eli Schwartz, Alok Srivastava, Michael Andrew Foynes, Eli Ben-David, Merav Davidson +10 more | 2021-10-26 |
| 10990419 | Dynamic multi monitor display and flexible tile display | Eli Schwartz, Michael Andrew Foynes, Alexander Vakaluk, Nir Levy, Irit Shalom Kantor +2 more | 2021-04-27 |
| 10936343 | In-context event orchestration of physical and cyber resources | Eli Schwartz, Alok Srivastava, Michael Andrew Foynes, Eli Ben-David, Merav Davidson +13 more | 2021-03-02 |
| 10782984 | Interactive event creation control console | Eli Schwartz, Michael Andrew Foynes, Alexander Vakaluk, Nir Levy, Irit Shalom Kantor +2 more | 2020-09-22 |
| 10740516 | Modifying circuits to prevent redundant switching | Giora Biran | 2020-08-11 |
| 9600616 | Assuring chip reliability with automatic generation of drivers and assertions | Erez Barak, Bodo Hoppe, Udo Krautz, Shiri Moran | 2017-03-21 |
| 9569582 | Template matching for resilience and security characteristics of sub-component chip designs | Pradip Bose, Prabhakar Kudva, Shiri Moran, K. Paul Muller | 2017-02-14 |
| 9483591 | Assuring chip reliability with automatic generation of drivers and assertions | Erez Barak, Bodo Hoppe, Udo Krautz, Shiri Moran | 2016-11-01 |
| 8949766 | Detecting corresponding paths in combinationally equivalent circuit designs | Oshri Adler, Ilan Beer | 2015-02-03 |
| 8713509 | Circuit design approximation | Oleg Rokhlenko | 2014-04-29 |
| 8589841 | Automatic parity checking identification | Sergey Novimov, Karen Frida Yorav | 2013-11-19 |
| 8539403 | Reducing observability of memory elements in circuits | Cynthia Rae Eisner, Oleg Rokhlenko, Karen Frida Yorav | 2013-09-17 |
| 8417507 | Formal verification of models using concurrent model-reduction and model-checking | Shaked Flur, Ziv Nevo, Michael Shamis | 2013-04-09 |
| 8365114 | Logic modification synthesis | David J. Geiger, Victor N. Kravets, Smita Krishnaswamy, Ruchir Puri, Haoxing Ren | 2013-01-29 |
| 8296256 | SAT-based synthesis of a clock gating function | Oleg Rokhlenko, Karen Frida Yorav | 2012-10-23 |
| 8261227 | Circuit design approximation | Oleg Rokhlenko | 2012-09-04 |
| 8244516 | Formal verification of models using concurrent model-reduction and model-checking | Shaked Flur, Ziv Nevo, Michael Shamis | 2012-08-14 |
| 8166444 | Clock gating using abstraction refinement | Cindy Eisner, Oleg Rokhlenko | 2012-04-24 |
| 8166426 | Approximation of a clock gating function via BDD path elimination | Oleg Rokhlenko | 2012-04-24 |
| 7676778 | Circuit design optimization of integrated circuit based clock gated memory elements | Cynthia Rae Eisner, Alexander Itskovich, Nicolas Maeding | 2010-03-09 |
| 7562325 | Device to cluster Boolean functions for clock gating | Oded Fuhrmann, Cynthia Rae Eisner, Alexander Itskovich, David J. Levitt | 2009-07-14 |
| 7458050 | Methods to cluster boolean functions for clock gating | Oded Fuhrmann, Cynthia Rae Eisner, Alexander Itskovich, David J. Levitt | 2008-11-25 |