Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7782114 | Design structure for a high-speed level shifter | Anirban Banerjee, Shiu Chung Ho | 2010-08-24 |
| 7564290 | Design structure for a high-speed level shifter | Anirban Banerjee, Shiu Chung Ho | 2009-07-21 |
| 7472320 | Autonomous self-monitoring and corrective operation of an integrated circuit | Zachary E. Berndlmaier, William R. Tonti | 2008-12-30 |
| 7042776 | Method and circuit for dynamic read margin control of a memory array | Miles G. Canada, Robert M. Houle, Dongho Lee, Vinod Ramadurai, Mathew I. Ringler +2 more | 2006-05-09 |
| 6888402 | Low voltage current reference circuits | — | 2005-05-03 |
| 6410962 | Structure for SOI wafers to avoid electrostatic discharge | Steven H. Voldman | 2002-06-25 |
| 6245600 | Method and structure for SOI wafers to avoid electrostatic discharge | Steven H. Voldman | 2001-06-12 |
| 5874337 | Method of forming eeprom cell with channel hot electron programming | — | 1999-02-23 |
| 5753951 | EEPROM cell with channel hot electron programming and method for forming the same | — | 1998-05-19 |
| 5629544 | Semiconductor diode with silicide films and trench isolation | Steven H. Voldman, Minh H. Tong, Edward J. Nowak | 1997-05-13 |
| 5498564 | Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction | David K. Lloyd, Matthew Paggi | 1996-03-12 |
| 5448090 | Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction | David K. Lloyd, Matthew Paggi | 1995-09-05 |
| 5434109 | Oxidation of silicon nitride in semiconductor devices | Josef W. Korejwa, Jerome B. Lasky, Pai-Hung Pan | 1995-07-18 |
| 5185294 | Boron out-diffused surface strap process | Chung H. Lam, Jerome B. Lasky, Craig M. Hill, James S. Nakos, Steven J. Holmes +1 more | 1993-02-09 |