Issued Patents All Time
Showing 1–25 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7266663 | Automatic cache activation and deactivation for power reduction | Jeffery S. Hines, Clark Debs Jeffries | 2007-09-04 |
| 6838323 | Diffusion resistor/capacitor (DRC) non-aligned MOSFET structure | Robert J. Gauthier, Jr., Edward J. Nowak, Xiaowei Tian, Steven H. Voldman | 2005-01-04 |
| 6664150 | Active well schemes for SOI technology | William F. Clark, Jr., Edward J. Nowak, Jed H. Rankin | 2003-12-16 |
| 6552396 | Matched transistors and methods for forming the same | Andres Bryant, William F. Clark, Jr., Edward J. Nowak | 2003-04-22 |
| 6528846 | Asymmetric high voltage silicon on insulator device design for input output circuits | Edward J. Nowak | 2003-03-04 |
| 6512269 | High-voltage high-speed SOI MOSFET | Andres Bryant, Edward J. Nowak | 2003-01-28 |
| 6498058 | SOI pass-gate disturb solution | Andres Bryant, Edward J. Nowak | 2002-12-24 |
| 6475838 | Methods for forming decoupling capacitors | Andres Bryant, William F. Clark, Jr., Edward J. Nowak | 2002-11-05 |
| 6469350 | Active well schemes for SOI technology | William F. Clark, Jr., Edward J. Nowak, Jed H. Rankin | 2002-10-22 |
| 6459106 | Dynamic threshold voltage devices with low gate to substrate resistance | Andres Bryant, Edward J. Nowak | 2002-10-01 |
| 6455766 | Contact-less probe of semiconductor wafers | Donald J. Cook, Edward J. Nowak | 2002-09-24 |
| 6436744 | Method and structure for creating high density buried contact for use with SOI processes for high performance logic | Andres Bryant, Jerome B. Lasky, Edward J. Nowak, Jed H. Rankin | 2002-08-20 |
| 6437594 | SOI pass gate leakage monitor | Ronald J. Bolam, Andres Bryant, Edward J. Nowak | 2002-08-20 |
| 6429056 | Dynamic threshold voltage devices with low gate to substrate resistance | Andres Bryant, Edward J. Nowak | 2002-08-06 |
| 6424174 | Low leakage logic gates | Edward J. Nowak | 2002-07-23 |
| 6404236 | Domino logic circuit having multiplicity of gate dielectric thicknesses | Kerry Bernstein, Andres Bryant, Robert J. Gauthier, Jr., Edward J. Nowak | 2002-06-11 |
| 6400171 | Method and system for processing integrated circuits | Andres Bryant, William D. K. Clark, Edward J. Nowak | 2002-06-04 |
| 6365484 | Method of forming semiconductor device with decoupling capacitance | Edward J. Nowak | 2002-04-02 |
| 6333230 | Scalable high-voltage devices | Andres Bryant, William F. Clark, Jr., Edward J. Nowak, Kirk D. Peterson | 2001-12-25 |
| 6300785 | Contact-less probe of semiconductor wafers | Donald J. Cook, Edward J. Nowak | 2001-10-09 |
| 6249029 | Device method for enhanced avalanche SOI CMOS | Andres Bryant, William F. Clark, Jr., John J. Ellis-Monaghan, Edward P. Maciejewski, Edward J. Nowak +1 more | 2001-06-19 |
| 6249028 | Operable floating gate contact for SOI with high Vt well | Andres Bryant, Edward J. Nowak | 2001-06-19 |
| 6239591 | Method and apparatus for monitoring SOI hysterises effects | Andres Bryant, Edward J. Nowak | 2001-05-29 |
| 6239649 | Switched body SOI (silicon on insulator) circuits and fabrication method therefor | Claude L. Bertin, John J. Ellis-Monaghan, Erik L. Hedberg, Terence B. Hook, Jack A. Mandelman +3 more | 2001-05-29 |
| 6200843 | High-voltage, high performance FETs | Andres Bryant, Edward J. Nowak | 2001-03-13 |