Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9310424 | Monitoring aging of silicon in an integrated circuit device | Malcolm S. Allen-Ware, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl +1 more | 2016-04-12 |
| 8713490 | Managing aging of silicon in an integrated circuit device | Malcolm S. Allen-Ware, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl +1 more | 2014-04-29 |
| 8227849 | Method and structure for creation of a metal insulator metal capacitor | Ebenezer E. Eshun, Douglas D. Coolbaugh, Keith E. Downes, Natalie B. Feilchenfeld, Zhong-Xiang He | 2012-07-24 |
| 7890893 | Design structure for semiconductor on-chip repair scheme for negative bias temperature instability | Tom C. Lee, Timothy D. Sullivan | 2011-02-15 |
| 7838958 | Semiconductor on-chip repair scheme for negative bias temperature instability | Tom C. Lee, Timothy D. Sullivan | 2010-11-23 |
| 7728372 | Method and structure for creation of a metal insulator metal capacitor | Ebenezer E. Eshun, Douglas D. Coolbaugh, Keith E. Downes, Natalie B. Feilchenfeld, Zhong-Xiang He | 2010-06-01 |
| 7541829 | Method for correcting for asymmetry of threshold voltage shifts | Terrance Wayne Kueper, David P. Paulsen, John E. Sheets, II | 2009-06-02 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability | Subhash B. Kulkami, Dominic J. Schepis | 2008-05-27 |
| 7298161 | Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability | Kerry Bernstein, Edward J. Nowak, Alvin W. Strong, Jody Van Horn, Ernest Y. Wu | 2007-11-20 |
| 6891359 | Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability | Kerry Bernstein, Edward J. Nowak, Alvin W. Strong, Jody Van Horn, Ernest Y. Wu | 2005-05-10 |
| 6879177 | Method and testing circuit for tracking transistor stress degradation | William Paul Hovis, Terrance Wayne Kueper | 2005-04-12 |
| 6563173 | Silicon-on-insulator chip having an isolation barrier for reliability | Subhash B. Kulkarni, Dominic J. Schepis | 2003-05-13 |
| 6492684 | Silicon-on-insulator chip having an isolation barrier for reliability | Subhash B. Kulkarni, Dominic J. Schepis | 2002-12-10 |
| 6437594 | SOI pass gate leakage monitor | Andres Bryant, Edward J. Nowak, Minh H. Tong | 2002-08-20 |
| 6281095 | Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability | Subhash B. Kulkarni, Dominic J. Schepis | 2001-08-28 |
| 6239469 | Method for fabrication of silicon on insulator substrates | Richard J. Evans, Anthony M. Palagonia | 2001-05-29 |
| 6194253 | Method for fabrication of silicon on insulator substrates | Richard J. Evans, Anthony M. Palagonia | 2001-02-27 |
| 6133610 | Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture | Subhash B. Kulkarni, Dominic J. Schepis | 2000-10-17 |
| 5804459 | Method for charge enhanced defect breakdown to improve yield and reliability | Albert J. Gregoritsch, Jr. | 1998-09-08 |