Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5498564 | Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction | Stephen F. Geissler, David K. Lloyd | 1996-03-12 |
| 5448090 | Structure for reducing parasitic leakage in a memory array with merged isolation and node trench construction | Stephen F. Geissler, David K. Lloyd | 1995-09-05 |