Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7886253 | Design structure for performing iterative synthesis of an integrated circuit design to attain power closure | Paul D. Kartschoke, John J. Reilly, Manikandan Viswanath | 2011-02-08 |
| 7873923 | Power gating logic cones | Paul D. Kartschoke, John J. Reilly, Manikandan Viswanath | 2011-01-18 |
| 7539968 | Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints | Paul D. Kartschoke, John J. Reilly, Manikandan Viswanath | 2009-05-26 |
| 7444609 | Method of optimizing customizable filler cells in an integrated circuit physical design process | Paul E. Dunn, George W. Rohrbaugh, III | 2008-10-28 |
| 7194715 | Method and system for performing static timing analysis on digital electronic circuits | Gerard M. Salem | 2007-03-20 |