Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417029 | Memory view for memory module | Puneet Arora, Ke Zhang, Mohit Madaan | 2025-09-16 |
| 11971818 | Memory view for non-volatile memory module | Puneet Arora | 2024-04-30 |
| 11966633 | Control algorithm generator for non-volatile memory module | Puneet Arora | 2024-04-23 |
| 10783299 | Simulation event reduction and power control during MBIST through clock tree management | Puneet Arora, Norman Robert Card | 2020-09-22 |
| 10706950 | Testing for memory error correction code logic | Patrick Gallagher | 2020-07-07 |
| 10706952 | Testing for memories during mission mode self-test | Patrick Gallagher | 2020-07-07 |
| 10699795 | System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property cores | Norman Robert Card | 2020-06-30 |
| 10593419 | Failing read count diagnostics for memory built-in self-test | Puneet Arora, Norman Robert Card | 2020-03-17 |
| 10541043 | On demand data stream controller for programming and executing operations in an integrated circuit | Carl Wisnesky, II, Patrick Gallagher, Norman Robert Card | 2020-01-21 |
| 10504607 | Multiple-channel, programmable fuse control unit | Puneet Arora, Norman Robert Card | 2019-12-10 |
| 10482989 | Dynamic diagnostics analysis for memory built-in self-test | Puneet Arora, Norman Robert Card | 2019-11-19 |
| 10395747 | Register-transfer level design engineering change order strategy | Puneet Arora, Norman Robert Card | 2019-08-27 |
| 10387598 | Verifying results in simulation through simulation add-on to support visualization of selected memory contents in real time | Norman Robert Card | 2019-08-20 |
| 10387599 | Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST) | Puneet Arora, Norman Robert Card | 2019-08-20 |
| 10319459 | Customizable built-in self-test testplans for memory units | Puneet Arora, Norman Robert Card | 2019-06-11 |
| 10192013 | Test logic at register transfer level in an integrated circuit design | Puneet Arora, Ankit Bandejia, Navneet Kaushik | 2019-01-29 |
| 10095822 | Memory built-in self-test logic in an integrated circuit design | Navneet Kaushik, Puneet Arora, Norman Robert Card | 2018-10-09 |
| 10007489 | Automated method identifying physical memories within a core or macro integrated circuit design | Puneet Arora, Norman Robert Card | 2018-06-26 |
| 9865362 | Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) | Puneet Arora, Norman Robert Card, Navneet Kaushik | 2018-01-09 |
| 9640280 | Power domain aware insertion methods and designs for testing and repairing memory | Puneet Arora, Navneet Kaushik, Norman Robert Card | 2017-05-02 |
| 8990749 | Method and apparatus for optimizing memory-built-in-self test | Puneet Arora, Navneet Kaushik, Norman Robert Card | 2015-03-24 |
| 8719761 | Method and apparatus for optimizing memory-built-in-self test | Norman Robert Card, Puneet Arora, Navneet Kaushik | 2014-05-06 |
| 8677196 | Low cost production testing for memory | Norman Robert Card, Hanumantha Raya, Puneet Arora | 2014-03-18 |
| 8296703 | Fault modeling for state retention logic | Krishna Vijaya Chakravadhanula, Brion Keller, Vivek Chickermane | 2012-10-23 |
| 8271226 | Testing state retention logic in low power systems | Krishna Vijaya Chakravadhanula, Patrick Gallagher, Vivek Chickermane, Puneet Arora | 2012-09-18 |