Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412014 | IC chip with IC design modification detection | Vivek Chickermane, Christos Papameletis, Brian Foutz | 2025-09-09 |
| 12307186 | Launch off shift process | Puneet Arora, Subhasish Mukherjee, Sarthak Singhal, Christos Papameletis, Brian Foutz | 2025-05-20 |
| 12007440 | Systems and methods for scan chain stitching | Puneet Arora, Subhasish Mukherjee, Sarthak Singhal, Christos Papameletis, Brian Foutz +2 more | 2024-06-11 |
| 11947887 | Test-point flop sharing with improved testability in a circuit design | Brian Foutz, Prateek Kumar Rai, Sarthak Singhal, Christos Papameletis, Vivek Chickermane | 2024-04-02 |
| 10996270 | System and method for multiple device diagnostics and failure grouping | Sameer Chakravarthy Chillarige, Joe Swenton, Anil Malik | 2021-05-04 |
| 10955470 | Method to improve testability using 2-dimensional exclusive or (XOR) grids | Brian Foutz, Christos Papameletis, Vivek Chickermane | 2021-03-23 |
| 10853100 | Systems and methods for creating learning-based personalized user interfaces | Sonam Kathpalia, Mehakpreet Kaur, Sameer Chakravarthy Chillarige | 2020-12-01 |
| 10775435 | Low-power shift with clock staggering | Christos Papameletis, Brian Foutz, Vivek Chickermane | 2020-09-15 |
| 10761131 | Method for optimally connecting scan segments in two-dimensional compression chains | Christos Papameletis, Brian Foutz, Vivek Chickermane | 2020-09-01 |
| 10551435 | 2D compression-based low power ATPG | Nitin Parimi, Patrick Gallagher, Vivek Chickermane, Brian Foutz | 2020-02-04 |
| 10528689 | Verification process for IJTAG based test pattern migration | Rajesh Khurana, Vivek Chickermane, Dhruv Dua | 2020-01-07 |
| 10331506 | SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores | Vivek Chickermane, Christos Papameletis, Brian Foutz | 2019-06-25 |
| 10325048 | Virtual directory navigation and debugging across multiple test configurations in the same session | Sameer Chakravarthy Chillarige, Sonam Kathpalia, Mehakpreet Kaur, James Allen | 2019-06-18 |
| 9817068 | Method and system for improving efficiency of sequential test compression using overscan | Vivek Chickermane, Brian Foutz, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more | 2017-11-14 |
| 9817069 | Method and system for construction of a highly efficient and predictable sequential test decompression logic | Steev Wilcox, Vivek Chickermane, Paul Alexander Cunningham, Brian Foutz | 2017-11-14 |
| 9606179 | Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer | Paul Alexander Cunningham, Steev Wilcox, Vivek Chickermane, Brian Foutz | 2017-03-28 |
| 9513335 | Method for using XOR trees for physically efficient scan compression and decompression logic | Steev Wilcox, Brian Foutz, Paul Alexander Cunningham, Vivek Chickermane | 2016-12-06 |
| 9470755 | Method for dividing testable logic into a two-dimensional grid for physically efficient scan | Brian Foutz, Steev Wilcox, Vivek Chickermane, Paul Alexander Cunningham | 2016-10-18 |
| 9470756 | Method for using sequential decompression logic for VLSI test in a physically efficient construction | Steev Wilcox, Brian Foutz, Vivek Chickermane, Paul Alexander Cunningham | 2016-10-18 |
| 9470754 | Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization | Vivek Chickermane, Brian Foutz, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more | 2016-10-18 |
| 9170301 | Hierarchical compaction for test pattern power generation | Patrick Gallagher, Rajesh Khurana | 2015-10-27 |
| 8904256 | Method and apparatus for low-pin count testing of integrated circuits | Vivek Chickermane, Dale Edward Meehl | 2014-12-02 |
| 8650524 | Method and apparatus for low-pin count testing of integrated circuits | Vivek Chickermane, Dale Edward Meehl | 2014-02-11 |
| 8615692 | Method and system for analyzing test vectors to determine toggle counts | Rajesh Khurana, Vivek Chickermane | 2013-12-24 |
| 8296694 | System and method for automated synthesis of circuit wrappers | Vivek Chickermane | 2012-10-23 |