Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12055586 | 3D stacked die testing structure | Sagar Kumar, Vivek Chickermane | 2024-08-06 |
| 11379644 | IC chip test engine | Divyank Mittal, Sagar Kumar, Vivek Chickermane | 2022-07-05 |
| 10796041 | Compacting test patterns for IJTAG test | Vivek Chickermane, Divyank Mittal, Balveer Singh Koranga | 2020-10-06 |
| 10528689 | Verification process for IJTAG based test pattern migration | Vivek Chickermane, Dhruv Dua, Krishna Vijaya Chakravadhanula | 2020-01-07 |
| 9170301 | Hierarchical compaction for test pattern power generation | Patrick Gallagher, Krishna Vijaya Chakravadhanula | 2015-10-27 |
| 8615692 | Method and system for analyzing test vectors to determine toggle counts | Krishna Vijaya Chakravadhanula, Vivek Chickermane | 2013-12-24 |