Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430474 | Locking mechanism and core wrapping for IP core | — | 2025-09-30 |
| 12412014 | IC chip with IC design modification detection | Christos Papameletis, Brian Foutz, Krishna Vijaya Chakravadhanula | 2025-09-09 |
| 12055586 | 3D stacked die testing structure | Sagar Kumar, Rajesh Khurana | 2024-08-06 |
| 11947887 | Test-point flop sharing with improved testability in a circuit design | Krishna Vijaya Chakravadhanula, Brian Foutz, Prateek Kumar Rai, Sarthak Singhal, Christos Papameletis | 2024-04-02 |
| 11379644 | IC chip test engine | Rajesh Khurana, Divyank Mittal, Sagar Kumar | 2022-07-05 |
| 11256839 | IP block scan chain construction | Subhasish Mukherjee | 2022-02-22 |
| 10955470 | Method to improve testability using 2-dimensional exclusive or (XOR) grids | Brian Foutz, Christos Papameletis, Krishna Vijaya Chakravadhanula | 2021-03-23 |
| 10796041 | Compacting test patterns for IJTAG test | Rajesh Khurana, Divyank Mittal, Balveer Singh Koranga | 2020-10-06 |
| 10775435 | Low-power shift with clock staggering | Christos Papameletis, Brian Foutz, Krishna Vijaya Chakravadhanula | 2020-09-15 |
| 10761131 | Method for optimally connecting scan segments in two-dimensional compression chains | Christos Papameletis, Brian Foutz, Krishna Vijaya Chakravadhanula | 2020-09-01 |
| 10747922 | Test circuitry with annularly arranged compressor and decompressor elements | Akhil Garg, Sahil Jain | 2020-08-18 |
| 10740515 | Devices and methods for test point insertion coverage | Jagjot Kaur, Priyanka Dasgupta, Gopi Kudva | 2020-08-11 |
| 10551435 | 2D compression-based low power ATPG | Nitin Parimi, Krishna Vijaya Chakravadhanula, Patrick Gallagher, Brian Foutz | 2020-02-04 |
| 10528689 | Verification process for IJTAG based test pattern migration | Rajesh Khurana, Dhruv Dua, Krishna Vijaya Chakravadhanula | 2020-01-07 |
| 10417363 | Power and scan resource reduction in integrated circuit designs having shift registers | Jagjot Kaur, Priyanka Dasgupta, Pratyush Aditya Kothamasu | 2019-09-17 |
| 10331506 | SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores | Christos Papameletis, Krishna Vijaya Chakravadhanula, Brian Foutz | 2019-06-25 |
| 10234504 | Optimizing core wrappers in an integrated circuit | Subhasish Mukherjee, Jagjot Kaur, Susan Marie Genova | 2019-03-19 |
| 9817069 | Method and system for construction of a highly efficient and predictable sequential test decompression logic | Steev Wilcox, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham, Brian Foutz | 2017-11-14 |
| 9817068 | Method and system for improving efficiency of sequential test compression using overscan | Krishna Vijaya Chakravadhanula, Brian Foutz, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more | 2017-11-14 |
| 9702934 | Reducing mask data volume with elastic compression | Dale Edward Meehl | 2017-07-11 |
| 9606179 | Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer | Paul Alexander Cunningham, Steev Wilcox, Krishna Vijaya Chakravadhanula, Brian Foutz | 2017-03-28 |
| 9513335 | Method for using XOR trees for physically efficient scan compression and decompression logic | Steev Wilcox, Brian Foutz, Paul Alexander Cunningham, Krishna Vijaya Chakravadhanula | 2016-12-06 |
| 9501590 | Systems and methods for testing integrated circuit designs | Paul Alexander Cunningham, Steev Wilcox | 2016-11-22 |
| 9470756 | Method for using sequential decompression logic for VLSI test in a physically efficient construction | Steev Wilcox, Brian Foutz, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham | 2016-10-18 |
| 9470755 | Method for dividing testable logic into a two-dimensional grid for physically efficient scan | Brian Foutz, Steev Wilcox, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham | 2016-10-18 |