Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412014 | IC chip with IC design modification detection | Vivek Chickermane, Christos Papameletis, Krishna Vijaya Chakravadhanula | 2025-09-09 |
| 12307186 | Launch off shift process | Puneet Arora, Subhasish Mukherjee, Sarthak Singhal, Christos Papameletis, Krishna Vijaya Chakravadhanula | 2025-05-20 |
| 12007440 | Systems and methods for scan chain stitching | Puneet Arora, Subhasish Mukherjee, Sarthak Singhal, Christos Papameletis, Krishna Vijaya Chakravadhanula +2 more | 2024-06-11 |
| 11947887 | Test-point flop sharing with improved testability in a circuit design | Krishna Vijaya Chakravadhanula, Prateek Kumar Rai, Sarthak Singhal, Christos Papameletis, Vivek Chickermane | 2024-04-02 |
| 10955470 | Method to improve testability using 2-dimensional exclusive or (XOR) grids | Christos Papameletis, Vivek Chickermane, Krishna Vijaya Chakravadhanula | 2021-03-23 |
| 10775435 | Low-power shift with clock staggering | Christos Papameletis, Vivek Chickermane, Krishna Vijaya Chakravadhanula | 2020-09-15 |
| 10761131 | Method for optimally connecting scan segments in two-dimensional compression chains | Christos Papameletis, Vivek Chickermane, Krishna Vijaya Chakravadhanula | 2020-09-01 |
| 10551435 | 2D compression-based low power ATPG | Nitin Parimi, Krishna Vijaya Chakravadhanula, Patrick Gallagher, Vivek Chickermane | 2020-02-04 |
| 10331506 | SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores | Vivek Chickermane, Christos Papameletis, Krishna Vijaya Chakravadhanula | 2019-06-25 |
| 9817069 | Method and system for construction of a highly efficient and predictable sequential test decompression logic | Steev Wilcox, Krishna Vijaya Chakravadhanula, Vivek Chickermane, Paul Alexander Cunningham | 2017-11-14 |
| 9817068 | Method and system for improving efficiency of sequential test compression using overscan | Vivek Chickermane, Krishna Vijaya Chakravadhanula, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more | 2017-11-14 |
| 9606179 | Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer | Paul Alexander Cunningham, Steev Wilcox, Vivek Chickermane, Krishna Vijaya Chakravadhanula | 2017-03-28 |
| 9513335 | Method for using XOR trees for physically efficient scan compression and decompression logic | Steev Wilcox, Paul Alexander Cunningham, Vivek Chickermane, Krishna Vijaya Chakravadhanula | 2016-12-06 |
| 9470754 | Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization | Vivek Chickermane, Krishna Vijaya Chakravadhanula, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more | 2016-10-18 |
| 9470755 | Method for dividing testable logic into a two-dimensional grid for physically efficient scan | Steev Wilcox, Vivek Chickermane, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham | 2016-10-18 |
| 9470756 | Method for using sequential decompression logic for VLSI test in a physically efficient construction | Steev Wilcox, Krishna Vijaya Chakravadhanula, Vivek Chickermane, Paul Alexander Cunningham | 2016-10-18 |
| 8001433 | Scan testing architectures for power-shutoff aware systems | Sandeep Bhatia, Patrick Gallagher, Vivek Chickermane | 2011-08-16 |
| 7979764 | Distributed test compression for integrated circuits | Patrick Gallagher, Vivek Chickermane, Carl Barnhart | 2011-07-12 |
| 7926012 | Design-For-testability planner | Nitin Parimi, Patrick Gallagher, Vivek Chickermane | 2011-04-12 |
| 6996515 | Enabling verification of a minimal level sensitive timing abstraction model | Martin Foltin, Sean Tyler | 2006-02-07 |
| 6611948 | Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model | Sean Tyler, Martin Foltin | 2003-08-26 |
| 6609233 | Load sensitivity modeling in a minimal level sensitive timing abstraction model | Martin Foltin, Sean Tyler | 2003-08-19 |
| 6604227 | Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools | Martin Foltin, Sean Tyler | 2003-08-05 |
| 6581197 | Minimal level sensitive timing representative of a circuit path | Martin Foltin, Sean Tyler | 2003-06-17 |