Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12254395 | System and method for processing convolutions on crossbar-based neural network accelerators for increased inference throughput | Glaucimar Da Silva Aguiar, Francisco Plinio Oliveira Silveira, Eun Sub Lee, Rodrigo Jose da Rosa Antunes, Joaquim Gomes Da Costa Eulalio De Souza +5 more | 2025-03-18 |
| 12242966 | Acceleration of model/weight programming in memristor crossbar arrays | Sai Rahul Chalamalasetti, Paolo Faraboschi, Catherine Graves, Dejan S. Milojicic, John Paul Strachan +1 more | 2025-03-04 |
| 12204961 | Resistive and digital processing cores | John Paul Strachan, Dejan S. Milojicic, Sai Rahul Chalamalasetti, Amit Sharma | 2025-01-21 |
| 12001183 | Scalable microservices-driven industrial IoT controller architecture | William E. White, Aalap Tripathy, Harvey Edward White, JR. | 2024-06-04 |
| 11947928 | Multi-die dot-product engine to provision large scale machine learning inference applications | Craig Warner, Eun Sub Lee, Sai Rahul Chalamalasetti | 2024-04-02 |
| 11861429 | Resistive and digital processing cores | John Paul Strachan, Dejan S. Milojicic, Sai Rahul Chalamalasetti, Amit Sharma | 2024-01-02 |
| 11853846 | Acceleration of model/weight programming in memristor crossbar arrays | Sai Rahul Chalamalasetti, Paolo Faraboschi, Catherine Graves, Dejan S. Milojicic, John Paul Strachan +1 more | 2023-12-26 |
| 11532356 | Self-healing dot-product engine | Amit Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner | 2022-12-20 |
| 11475169 | Security and anomaly detection for Internet-of-Things devices | Aalap Tripathy, Harvey Edward White, JR., John Paul Strachan | 2022-10-18 |
| 11385863 | Adjustable precision for multi-stage compute processes | Sai Rahul Chalamalasetti, Paolo Faraboschi, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov +1 more | 2022-07-12 |
| 11322545 | Vertical JFET device for memristor array interface | Amit Sharma, John Paul Strachan | 2022-05-03 |
| 11294763 | Determining significance levels of error values in processes that include multiple layers | John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Sergey Serebryakov | 2022-04-05 |
| 11024379 | Methods and systems for highly optimized memristor write process | Amit Sharma, John Paul Strachan, Suhas Kumar, Catherine Graves, Craig Warner | 2021-06-01 |
| 10984860 | Self-healing dot-product engine | Amit Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner | 2021-04-20 |
| 10983865 | Adjusting memory parameters | Gregg B. Lesartre | 2021-04-20 |
| 10735030 | Re-encoding data associated with failed memory devices | Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen | 2020-08-04 |
| 10671291 | Iterative write sequence interrupt | Gregg B. Lesartre | 2020-06-02 |
| 10490270 | Reference column sensing for resistive memory | James S. Ignowski, Yoocharn Jeon | 2019-11-26 |
| 10460800 | Data sensing in crosspoint memory structures | Gregg B. Lesartre, Yoocharn Jeon | 2019-10-29 |
| 10452472 | Tunable and dynamically adjustable error correction for memristor crossbars | Catherine Graves, John Paul Strachan, Dejan S. Milojicic, Paolo Faraboschi, Sergey Serebryakov | 2019-10-22 |
| 10318205 | Managing data using a number of non-volatile memory arrays | Gregg B. Lesartre | 2019-06-11 |
| 10312943 | Error correction code in memory | Gregg B. Lesartre, Craig Warner, Chris Michael Brueggen, Brian S. Birk, Harvey Ray | 2019-06-04 |
| 10275307 | Detection of error patterns in memory dies | Gregg B. Lesartre, Craig Warner, Chris Michael Brueggen | 2019-04-30 |
| 10191884 | Managing a multi-lane serial link | Gregg B. Lesartre | 2019-01-29 |
| 10157668 | Memristance feedback tuning | Luke Whitaker, Emmanuelle J. Merced Grafals | 2018-12-18 |