Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10056140 | Memristor memory with volatile and non-volatile states | Yoocharn Jeon | 2018-08-21 |
| 9972387 | Sensing circuit for resistive memory | Yoocharn Jeon, Brent Buchanan, Erik Ordentlich, Naveen Muralimanohar, James S. Ignowski +1 more | 2018-05-15 |
| 9773547 | Non-volatile memory with multiple latency tiers | Richard H. Henze, Naveen Muralimanohar, Yoocharn Jeon, Erik Ordentlich, Gregg B. Lesartre +1 more | 2017-09-26 |
| 9767901 | Circuits having selector devices with different I-V responses | Amit Sharma, Gary Gibson, Naveen Muralimanohar, Greg Astfalk | 2017-09-19 |
| 9754666 | Resistive ratio-based memory cell | Brent Buchanan, Jeffrey A. Lucas, Clinton Harold Parker | 2017-09-05 |
| 9146848 | Link training for a serdes link | Gregg B. Lesartre | 2015-09-29 |
| 6996515 | Enabling verification of a minimal level sensitive timing abstraction model | Brian Foutz, Sean Tyler | 2006-02-07 |
| 6611948 | Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model | Sean Tyler, Brian Foutz | 2003-08-26 |
| 6609233 | Load sensitivity modeling in a minimal level sensitive timing abstraction model | Brian Foutz, Sean Tyler | 2003-08-19 |
| 6604227 | Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools | Brian Foutz, Sean Tyler | 2003-08-05 |
| 6581197 | Minimal level sensitive timing representative of a circuit path | Brian Foutz, Sean Tyler | 2003-06-17 |