Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10922178 | Masterless raid for byte-addressable non-volatile memory | Gregg B. Lesartre, Russ W. Herrell | 2021-02-16 |
| 10735030 | Re-encoding data associated with failed memory devices | Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Martin Foltin | 2020-08-04 |
| 10666294 | Error correction code words with binomial bit error distribution | — | 2020-05-26 |
| 10567003 | List decode circuits | — | 2020-02-18 |
| 10402287 | Preventing data corruption and single point of failure in a fault-tolerant memory | Derek Alan Sherlock, Harvey Ray | 2019-09-03 |
| 10367529 | List decode circuits | Ron M. Roth | 2019-07-30 |
| 10312943 | Error correction code in memory | Gregg B. Lesartre, Craig Warner, Martin Foltin, Brian S. Birk, Harvey Ray | 2019-06-04 |
| 10275307 | Detection of error patterns in memory dies | Gregg B. Lesartre, Craig Warner, Martin Foltin | 2019-04-30 |
| 10243587 | Managing results from list decode methods | Cesar Garzon, Jonathan Edward George | 2019-03-26 |
| 10176043 | Memory controller | Gregg B. Lesartre, Lidia Warnes | 2019-01-08 |
| 10050641 | List manipulation circuits | — | 2018-08-14 |
| 8521940 | Paired node controllers | — | 2013-08-27 |
| 8370582 | Merging subsequent updates to a memory location | — | 2013-02-05 |
| 8316189 | Rescinding ownership of a cache line in a computer system | — | 2012-11-20 |
| 8085801 | Resource arbitration | — | 2011-12-27 |
| 7817653 | Priority selection circuit | — | 2010-10-19 |
| 7237176 | Partitioning data for error correction | Theodore Briggs, Jay Tsao | 2007-06-26 |