JK

Jagjot Kaur

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
📍 Milpitas, CA: #1,077 of 3,192 inventorsTop 35%
🗺 California: #124,610 of 386,348 inventorsTop 35%
Overall (All Time): #1,145,863 of 4,157,543Top 30%
4
Patents All Time

Issued Patents All Time

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
11409931 Systems and methods for optimizing scan pipelining in hierarchical test design William Gaskins 2022-08-09
10740515 Devices and methods for test point insertion coverage Priyanka Dasgupta, Vivek Chickermane, Gopi Kudva 2020-08-11
10417363 Power and scan resource reduction in integrated circuit designs having shift registers Priyanka Dasgupta, Pratyush Aditya Kothamasu, Vivek Chickermane 2019-09-17
10234504 Optimizing core wrappers in an integrated circuit Subhasish Mukherjee, Vivek Chickermane, Susan Marie Genova 2019-03-19