PD

Priyanka Dasgupta

CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
Overall (All Time): #1,915,420 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10740515 Devices and methods for test point insertion coverage Jagjot Kaur, Vivek Chickermane, Gopi Kudva 2020-08-11
10417363 Power and scan resource reduction in integrated circuit designs having shift registers Jagjot Kaur, Pratyush Aditya Kothamasu, Vivek Chickermane 2019-09-17