KC

Krishna Vijaya Chakravadhanula

CS Cadence Design Systems: 27 patents #17 of 2,263Top 1%
📍 Vestal, NY: #25 of 481 inventorsTop 6%
🗺 New York: #4,646 of 115,490 inventorsTop 5%
Overall (All Time): #142,342 of 4,157,543Top 4%
27
Patents All Time

Issued Patents All Time

Showing 26–27 of 27 patents

Patent #TitleCo-InventorsDate
8296703 Fault modeling for state retention logic Steven Lee Gregor, Brion Keller, Vivek Chickermane 2012-10-23
8271226 Testing state retention logic in low power systems Patrick Gallagher, Vivek Chickermane, Steven Lee Gregor, Puneet Arora 2012-09-18