Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7168005 | Programable multi-port memory BIST with compact microcode | R. Dean Adams, Thomas J. Eckenrode, Kamran Zarrineh | 2007-01-23 |
| 7032144 | Method and apparatus for testing multi-port memories | R. Dean Adams, Thomas J. Eckenrode, Kamran Zarrineh | 2006-04-18 |
| 7003704 | Two-dimensional redundancy calculation | R. Dean Adams, Thomas J. Eckenrode, Garrett Stephen Koch | 2006-02-21 |
| 6907554 | Built-in self test system and method for two-dimensional memory redundancy allocation | R. Dean Adams, Thomas J. Eckenrode, Gary S. Koch | 2005-06-14 |
| 6874111 | System initialization of microcode-based memory built-in self-test | R. Dean Adams, Thomas J. Eckenrode, Kamran Zarrineh | 2005-03-29 |
| 6651201 | Programmable memory built-in self-test combining microcode and finite state machine self-test | R. Dean Adams, Thomas J. Eckenrode, Kamran Zarrineh | 2003-11-18 |
| 6557127 | Method and apparatus for testing multi-port memories | R. Dean Adams, Thomas J. Eckenrode, Kamran Zarrineh | 2003-04-29 |
| 6490660 | Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system | Glenn D. Gilda | 2002-12-03 |
| 6161208 | Storage subsystem including an error correcting cache and means for performing memory to memory transfers | Patrick F. Dutton, Hehching Harry Li | 2000-12-12 |
| 6115795 | Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system | Glenn D. Gilda | 2000-09-05 |
| 5909694 | Multiway associative external microprocessor cache | Thomas L. Jeremiah | 1999-06-01 |
| 5860138 | Processor with compiler-allocated, variable length intermediate storage | David R. Engebretsen, Mayan Moudgill, John C. Willis | 1999-01-12 |
| 5553305 | System for synchronizing execution by a processing element of threads within a process using a state indicator | Robert Iannucci | 1996-09-03 |
| 5450563 | Storage protection keys in two level cache system | — | 1995-09-12 |
| 5313613 | Execution of storage-immediate and storage-storage instructions within cache buffer storage | — | 1994-05-17 |
| 5276848 | Shared two level cache including apparatus for maintaining storage consistency | Patrick Gallagher, Stephen Reeve | 1994-01-04 |
| 5226169 | System for execution of storage-immediate and storage-storage instructions within cache buffer storage | — | 1993-07-06 |
| 5023776 | Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage | — | 1991-06-11 |
| 4924466 | Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system | Victor Lee | 1990-05-08 |