Issued Patents All Time
Showing 25 most recent of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165030 | System and architecture including processor and neural network accelerator | John Glossner | 2024-12-10 |
| 12050910 | Device and method for hardware-efficient adaptive calculation of floating-point trigonometric functions using coordinate rotate digital computer (CORDIC) | Pablo Balzola, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal | 2024-07-30 |
| 11928465 | Device and method for calculating elementary functions using successive cumulative rotation circuit | Pablo Balzola, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal | 2024-03-12 |
| 11650817 | System and method to implement masked vector instructions | Murugappan Senthilvelan | 2023-05-16 |
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2023-01-03 |
| 11157407 | Implementing atomic primitives using cache line locking | A. Joseph Hoane | 2021-10-26 |
| 11144815 | System and architecture of neural network accelerator | John Glossner | 2021-10-12 |
| 10922267 | Vector processor to operate on variable length vectors using graphics processing instructions | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Vitaly Kalashnikov, Sitij Agrawal | 2021-02-16 |
| 10908909 | Processor with mode support | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan | 2021-02-02 |
| 10846259 | Vector processor to operate on variable length vectors with out-of-order execution | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan, Pablo Balzola | 2020-11-24 |
| 10824586 | Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Sitij Agrawal | 2020-11-03 |
| 10733140 | Vector processor configured to operate on variable length vectors using instructions that change element widths | Arthur Joseph Hoane, Paul Hurtley | 2020-08-04 |
| 10719451 | Variable translation-lookaside buffer (TLB) indexing | A. Joseph Hoane, Lei Wang, Gary J. Nacer, Aaron G. Milbury, Enrique A. Barria +1 more | 2020-07-21 |
| 10514915 | Computer processor with address register file | Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2019-12-24 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10169039 | Computer processor that implements pre-translation of virtual addresses | Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2019-01-01 |
| 9959246 | Vector processor configured to operate on variable length vectors using implicitly typed instructions | C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Vitaly Kalashnikov | 2018-05-01 |
| 9940129 | Computer processor with register direct branches and employing an instruction preload structure | Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2018-04-10 |
| 9910824 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2018-03-06 |
| 9792116 | Computer processor that implements pre-translation of virtual addresses with target registers | Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2017-10-17 |
| 9146708 | Implementation of arbitrary galois field arithmetic on a programmable processor | — | 2015-09-29 |
| 9110726 | Method and system for parallelization of pipelined computations | Vladimir Kotlyar, Yurly M. Pogudin | 2015-08-18 |
| 8959315 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Michael Schulte, C. John Glossner | 2015-02-17 |
| 8918627 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Michael Schulte, C. John Glossner | 2014-12-23 |