Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2023-01-03 |
| 10922267 | Vector processor to operate on variable length vectors using graphics processing instructions | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Vitaly Kalashnikov, Sitij Agrawal | 2021-02-16 |
| 10908909 | Processor with mode support | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan | 2021-02-02 |
| 10846259 | Vector processor to operate on variable length vectors with out-of-order execution | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Murugappan Senthilvelan, Pablo Balzola | 2020-11-24 |
| 10824586 | Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Sitij Agrawal | 2020-11-03 |
| 10514915 | Computer processor with address register file | Mayan Moudgill, Gary J. Nacer, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2019-12-24 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more | 2019-07-02 |
| 10169039 | Computer processor that implements pre-translation of virtual addresses | Mayan Moudgill, Gary J. Nacer, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2019-01-01 |
| 9959246 | Vector processor configured to operate on variable length vectors using implicitly typed instructions | Mayan Moudgill, Arthur Joseph Hoane, Paul Hurtley, Vitaly Kalashnikov | 2018-05-01 |
| 9940129 | Computer processor with register direct branches and employing an instruction preload structure | Mayan Moudgill, Gary J. Nacer, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2018-04-10 |
| 9910824 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Mayan Moudgill, Gary J. Nacer, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2018-03-06 |
| 9792116 | Computer processor that implements pre-translation of virtual addresses with target registers | Mayan Moudgill, Gary J. Nacer, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more | 2017-10-17 |
| 9766894 | Method and apparatus for enabling a processor to generate pipeline control signals | Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-09-19 |
| 9766895 | Opportunity multithreading in a multithreaded processor with instruction chaining capability | Shenghong Wang, Gary J. Nacer | 2017-09-19 |
| 9558000 | Multithreading using an ordered list of hardware contexts | Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-01-31 |
| 8959315 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2015-02-17 |
| 8918627 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2014-12-23 |
| 8892849 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2014-11-18 |
| 8762688 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2014-06-24 |
| 8074051 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2011-12-06 |
| 7797363 | Processor having parallel vector multiply and reduce operations with sequential semantics | Erdem Hokenek, Michael Schulte, Mayan Moudgill | 2010-09-14 |
| 7593978 | Processor reduction unit for accumulation of multiple operands with or without saturation | Michael Schulte, Pablo Balzola | 2009-09-22 |
| 7475222 | Multi-threaded processor having compound instruction and operation formats | Erdem Hokenek, Mayan Moudgill, Michael Schulte | 2009-01-06 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection | Michael Schulte, Erdem Hokenek, Pablo Balzola | 2008-09-23 |