| 11544214 |
Monolithic vector processor configured to operate on variable length vectors using a vector length register |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +3 more |
2023-01-03 |
| 10922267 |
Vector processor to operate on variable length vectors using graphics processing instructions |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Vitaly Kalashnikov, Sitij Agrawal |
2021-02-16 |
| 10908909 |
Processor with mode support |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan |
2021-02-02 |
| 10846259 |
Vector processor to operate on variable length vectors with out-of-order execution |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Murugappan Senthilvelan, Pablo Balzola |
2020-11-24 |
| 10824586 |
Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Sitij Agrawal |
2020-11-03 |
| 10733140 |
Vector processor configured to operate on variable length vectors using instructions that change element widths |
Mayan Moudgill, Paul Hurtley |
2020-08-04 |
| 10339094 |
Vector processor configured to operate on variable length vectors with asymmetric multi-threading |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +3 more |
2019-07-02 |
| 10339095 |
Vector processor configured to operate on variable length vectors using digital signal processing instructions |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +3 more |
2019-07-02 |
| 9959246 |
Vector processor configured to operate on variable length vectors using implicitly typed instructions |
Mayan Moudgill, C. John Glossner, Paul Hurtley, Vitaly Kalashnikov |
2018-05-01 |
| 9910824 |
Vector processor configured to operate on variable length vectors using instructions to combine and split vectors |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +1 more |
2018-03-06 |
| 9766894 |
Method and apparatus for enabling a processor to generate pipeline control signals |
C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Paul D'Arcy +2 more |
2017-09-19 |
| 9558000 |
Multithreading using an ordered list of hardware contexts |
C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Vitaly Kalashnikov, Paul D'Arcy +2 more |
2017-01-31 |
| 8762641 |
Method for achieving power savings by disabling a valid array |
— |
2014-06-24 |
| 6990557 |
Method and apparatus for multithreaded cache with cache eviction based on thread identifier |
Erdem Hokenek, C. John Glossner, Mayan Moudgill, Shenghong Wang |
2006-01-24 |
| 6912623 |
Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy |
Erdem Hokenek, C. John Glossner, Mayan Moudgill, Shenghong Wang |
2005-06-28 |
| 5715391 |
Modular and infinitely extendable three dimensional torus packaging scheme for parallel processing |
Rory Jackson |
1998-02-03 |
