| 11544214 |
Monolithic vector processor configured to operate on variable length vectors using a vector length register |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more |
2023-01-03 |
| 10922267 |
Vector processor to operate on variable length vectors using graphics processing instructions |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Vitaly Kalashnikov, Sitij Agrawal |
2021-02-16 |
| 10908909 |
Processor with mode support |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan |
2021-02-02 |
| 10846259 |
Vector processor to operate on variable length vectors with out-of-order execution |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan, Pablo Balzola |
2020-11-24 |
| 10824586 |
Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Sitij Agrawal |
2020-11-03 |
| 10719451 |
Variable translation-lookaside buffer (TLB) indexing |
Mayan Moudgill, A. Joseph Hoane, Lei Wang, Aaron G. Milbury, Enrique A. Barria +1 more |
2020-07-21 |
| 10514915 |
Computer processor with address register file |
Mayan Moudgill, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more |
2019-12-24 |
| 10339094 |
Vector processor configured to operate on variable length vectors with asymmetric multi-threading |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more |
2019-07-02 |
| 10339095 |
Vector processor configured to operate on variable length vectors using digital signal processing instructions |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +3 more |
2019-07-02 |
| 10169039 |
Computer processor that implements pre-translation of virtual addresses |
Mayan Moudgill, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more |
2019-01-01 |
| 9940129 |
Computer processor with register direct branches and employing an instruction preload structure |
Mayan Moudgill, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more |
2018-04-10 |
| 9910824 |
Vector processor configured to operate on variable length vectors using instructions to combine and split vectors |
Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more |
2018-03-06 |
| 9792116 |
Computer processor that implements pre-translation of virtual addresses with target registers |
Mayan Moudgill, C. John Glossner, A. Joseph Hoane, Paul Hurtley, Murugappan Senthilvelan +1 more |
2017-10-17 |
| 9766894 |
Method and apparatus for enabling a processor to generate pipeline control signals |
C. John Glossner, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more |
2017-09-19 |
| 9766895 |
Opportunity multithreading in a multithreaded processor with instruction chaining capability |
Shenghong Wang, C. John Glossner |
2017-09-19 |
| 9558000 |
Multithreading using an ordered list of hardware contexts |
C. John Glossner, Murugappan Senthilvelan, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more |
2017-01-31 |
| 8471597 |
Power saving circuit using a clock buffer and multiple flip-flops |
Shenghong Wang, Mayan Moudgill |
2013-06-25 |
| 7158583 |
Multiple communication protocols with common sampling rate |
Daniel Iancu, Stuart G. Stanley |
2007-01-02 |