NK

Navneet Kaushik

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
CS Candence Design Systems: 1 patents #1 of 20Top 5%
Overall (All Time): #833,687 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
10192013 Test logic at register transfer level in an integrated circuit design Puneet Arora, Ankit Bandejia, Steven Lee Gregor 2019-01-29
10095822 Memory built-in self-test logic in an integrated circuit design Puneet Arora, Steven Lee Gregor, Norman Robert Card 2018-10-09
9865362 Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) Puneet Arora, Steven Lee Gregor, Norman Robert Card 2018-01-09
9640280 Power domain aware insertion methods and designs for testing and repairing memory Puneet Arora, Steven Lee Gregor, Norman Robert Card 2017-05-02
8990749 Method and apparatus for optimizing memory-built-in-self test Puneet Arora, Steven Lee Gregor, Norman Robert Card 2015-03-24
8719761 Method and apparatus for optimizing memory-built-in-self test Norman Robert Card, Puneet Arora, Steven Lee Gregor 2014-05-06