Issued Patents All Time
Showing 25 most recent of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12020736 | Spin-orbit-torque magnetoresistive random-access memory array | Daniel C. Worledge, Pouya Hashemi | 2024-06-25 |
| 11037645 | Dynamic boosting techniques for memory | Kotb Jabeur | 2021-06-15 |
| 10839935 | Dynamic redundancy for memory | Daniel C. Worledge, Kotb Jabeur, Matthew R. Wordeman | 2020-11-17 |
| 10741232 | Tunable reference system with sense amplifier offset cancellation for magnetic random access memory | Kotb Jabeur | 2020-08-11 |
| 10726897 | Trimming MRAM sense amp with offset cancellation | Thomas M. Maffitt, Matthew R. Wordeman | 2020-07-28 |
| 10437665 | Bad bit register for memory | Daniel C. Worledge | 2019-10-08 |
| 10394647 | Bad bit register for memory | Daniel C. Worledge | 2019-08-27 |
| 10374152 | Magnetic tunnel junction based anti-fuses with cascoded transistors | Anthony J. Annunziata, Chandrasekharan Kothandaraman | 2019-08-06 |
| 10360958 | Dual power rail cascode driver | Yutaka Nakamura | 2019-07-23 |
| 10229722 | Three terminal spin hall MRAM | Jonathan Zanhong Sun, Daniel C. Worledge | 2019-03-12 |
| 10170178 | Secure off-chip MRAM | William E. Hall, Hillery C. Hunter, Jeffrey A. Stuecheli, Daniel C. Worledge | 2019-01-01 |
| 10115450 | Cascode complimentary dual level shifter | Yutaka Nakamura | 2018-10-30 |
| 9917601 | Adaptive error correction in a memory system | Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari | 2018-03-13 |
| 9875780 | STT MRAM source line configuration | — | 2018-01-23 |
| 9852784 | Bit line clamp voltage generator for STT MRAM sensing | — | 2017-12-26 |
| 9823858 | Nonvolatile memory interface for metadata shadowing | Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge | 2017-11-21 |
| 9799386 | STT MRAM midpoint reference cell allowing full write | Matthew R. Wordeman | 2017-10-24 |
| 9792052 | Nonvolatile memory interface for metadata shadowing | Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge | 2017-10-17 |
| 9786343 | STT MRAM common source line array bias scheme | — | 2017-10-10 |
| 9666258 | Bit line clamp voltage generator for STT MRAM sensing | — | 2017-05-30 |
| 9613674 | Mismatch and noise insensitive sense amplifier circuit for STT MRAM | — | 2017-04-04 |
| 9569109 | Nonvolatile memory interface for metadata shadowing | Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge | 2017-02-14 |
| 9536926 | Magnetic tunnel junction based anti-fuses with cascoded transistors | Anthony J. Annunziata, Chandrasekharan Kothandaraman | 2017-01-03 |
| 9495242 | Adaptive error correction in a memory system | Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari | 2016-11-15 |
| 9496018 | Nonvolatile memory interface for metadata shadowing | Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge | 2016-11-15 |