Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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John K. DeBrosse — 93 Patents

IBM: 91 patents #672 of 70,183Top 1%
Infineon Technologies Ag: 7 patents #1,301 of 7,486Top 20%
MTMagic Technologies: 5 patents #17 of 54Top 35%
HTHeadway Technologies: 2 patents #181 of 309Top 60%
Kabushiki Kaisha Toshiba: 2 patents #10,039 of 21,451Top 50%
Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Colchester, VT: #8 of 432 inventorsTop 2%
Vermont: #58 of 4,968 inventorsTop 2%
Overall (All Time): #16,773 of 4,157,543Top 1%
93 Patents All Time
John K. DeBrosse has been granted 93 US patents while listed as an inventor at IBM. The first was granted in 1989 and the most recent in June 2024. John K. DeBrosse ranks #16,773 of 4,157,543 US inventors in our database (top 0.40%). Patent records list John K. DeBrosse in Colchester, VT, US.

Issued Patents All Time

Showing 1–25 of 93 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12020736 Spin-orbit-torque magnetoresistive random-access memory array Daniel C. Worledge, Pouya Hashemi 2024-06-25 $10,690,000
11037645 Dynamic boosting techniques for memory Kotb Jabeur 2021-06-15 $4,393,000
10839935 Dynamic redundancy for memory Daniel C. Worledge, Kotb Jabeur, Matthew R. Wordeman 2020-11-17 $2,639,000
10741232 Tunable reference system with sense amplifier offset cancellation for magnetic random access memory Kotb Jabeur 2020-08-11 $2,122,000
10726897 Trimming MRAM sense amp with offset cancellation Thomas M. Maffitt, Matthew R. Wordeman 2020-07-28 $3,400,000
10437665 Bad bit register for memory Daniel C. Worledge 2019-10-08 $4,743,000
10394647 Bad bit register for memory Daniel C. Worledge 2019-08-27 $1,335,000
10374152 Magnetic tunnel junction based anti-fuses with cascoded transistors Anthony J. Annunziata, Chandrasekharan Kothandaraman 2019-08-06 $1,880,000
10360958 Dual power rail cascode driver Yutaka Nakamura 2019-07-23 $2,519,000
10229722 Three terminal spin hall MRAM Jonathan Zanhong Sun, Daniel C. Worledge 2019-03-12 $2,141,000
10170178 Secure off-chip MRAM William E. Hall, Hillery C. Hunter, Jeffrey A. Stuecheli, Daniel C. Worledge 2019-01-01
10115450 Cascode complimentary dual level shifter Yutaka Nakamura 2018-10-30 $2,799,000
9917601 Adaptive error correction in a memory system Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari 2018-03-13 $2,527,000
9875780 STT MRAM source line configuration 2018-01-23 $4,886,000
9852784 Bit line clamp voltage generator for STT MRAM sensing 2017-12-26 $2,704,000
9823858 Nonvolatile memory interface for metadata shadowing Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge 2017-11-21 $3,803,000
9799386 STT MRAM midpoint reference cell allowing full write Matthew R. Wordeman 2017-10-24 $3,030,000
9792052 Nonvolatile memory interface for metadata shadowing Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge 2017-10-17 $4,096,000
9786343 STT MRAM common source line array bias scheme 2017-10-10 $2,342,000
9666258 Bit line clamp voltage generator for STT MRAM sensing 2017-05-30 $1,983,000
9613674 Mismatch and noise insensitive sense amplifier circuit for STT MRAM 2017-04-04 $2,713,000
9569109 Nonvolatile memory interface for metadata shadowing Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge 2017-02-14 $1,939,000
9536926 Magnetic tunnel junction based anti-fuses with cascoded transistors Anthony J. Annunziata, Chandrasekharan Kothandaraman 2017-01-03 $2,646,000
9495242 Adaptive error correction in a memory system Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari 2016-11-15 $2,170,000
9496018 Nonvolatile memory interface for metadata shadowing Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge 2016-11-15 $2,170,000