Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9478736 | Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns | Chung H. Lam, Janusz J. Nowak | 2016-10-25 |
| 9471422 | Adaptive error correction in a memory system | Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Rona Yaari | 2016-10-18 |
| 9450179 | Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy | Janusz J. Nowak | 2016-09-20 |
| 9384792 | Offset-cancelling self-reference STT-MRAM sense amplifier | Anthony R. Bonaccio, Thomas M. Maffitt | 2016-07-05 |
| 9378795 | Mismatch and noise insensitive sense amplifier circuit for STT MRAM | — | 2016-06-28 |
| 9373783 | Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy | Janusz J. Nowak | 2016-06-21 |
| 9373383 | STT-MRAM sensing technique | — | 2016-06-21 |
| 9355700 | Read circuit for memory | Jonathan Zanhong Sun, Po-Kang Wang | 2016-05-31 |
| 9343131 | Mismatch and noise insensitive sense amplifier circuit for STT MRAM | — | 2016-05-17 |
| 9105342 | Read circuit for memory | Jonathan Zanhong Sun, Po-Kang Wang | 2015-08-11 |
| 9065035 | Cell design for embedded thermally-assisted MRAM | Anthony J. Annunziata | 2015-06-23 |
| 8917531 | Cell design for embedded thermally-assisted MRAM | Anthony J. Annunziata | 2014-12-23 |
| 8901529 | Memory array with self-aligned epitaxially grown memory elements and annular FET | Chung H. Lam, Janusz J. Nowak | 2014-12-02 |
| 8835256 | Memory array with self-aligned epitaxially grown memory elements and annular FET | Chung H. Lam, Janusz J. Nowak | 2014-09-16 |
| 8828743 | Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns | Chung H. Lam, Janusz J. Nowak | 2014-09-09 |
| 8755213 | Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming | Kailash Gopalakrishnan, Chung H. Lam, Jing Li | 2014-06-17 |
| 8654577 | Shared bit line SMT MRAM array with shunting transistors between bit lines | Hsu Kai Yang, Yutaka Nakamura | 2014-02-18 |
| 8576618 | Shared bit line SMT MRAM array with shunting transistors between bit lines | Hsu Kai Yang, Yutaka Nakamura | 2013-11-05 |
| 8570793 | Shared bit line SMT MRAM array with shunting transistors between bit lines | Hsu Kai Yang, Yutaka Nakamura | 2013-10-29 |
| 8565014 | Shared bit line SMT MRAM array with shunting transistors between bit lines | Hsu Kai Yang, Yutaka Nakamura | 2013-10-22 |
| 8456901 | Spin-torque transfer magneto-resistive memory architecture | Yutaka Nakamura | 2013-06-04 |
| 8456899 | Spin-torque transfer magneto-resistive memory architecture | Yutaka Nakamura | 2013-06-04 |
| 8446757 | Spin-torque transfer magneto-resistive memory architecture | Yutaka Nakamura | 2013-05-21 |
| 8437181 | Shared bit line SMT MRAM array with shunting transistors between the bit lines | Hsu Kai Yang, Yutaka Nakamura | 2013-05-07 |
| 8370714 | Reference cells for spin torque based memory device | Daniel C. Worledge | 2013-02-05 |