Hsu Kai Yang — 33 Patents at Magic Technologies

Hsu Kai Yang has been granted 33 US patents while listed as an inventor at Magic Technologies. The first was granted in 2001 and the most recent in November 2024. Hsu Kai Yang ranks #105,480 of 4,157,543 US inventors in our database (top 2.5%). Patent records list Hsu Kai Yang in Pleasanton, CA, US.

Issued Patents All Time

Showing 1–25 of 33 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12153085	Massively independent testers system	—	2024-11-26
11396106	Hair cutting device adapted for cutting one's own hair	Luke Tzenmin Luangrath, Jerin Tzenjie Luangrath	2022-07-26
9170879	Method and apparatus for scrubbing accumulated data errors from a memory system	—	2015-10-27
8775865	Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits	—	2014-07-08
8654577	Shared bit line SMT MRAM array with shunting transistors between bit lines	Yutaka Nakamura, John K. DeBrosse	2014-02-18	$4,910,000
8576618	Shared bit line SMT MRAM array with shunting transistors between bit lines	Yutaka Nakamura, John K. DeBrosse	2013-11-05	$5,290,000
8570793	Shared bit line SMT MRAM array with shunting transistors between bit lines	Yutaka Nakamura, John K. DeBrosse	2013-10-29	$6,299,000
8565014	Shared bit line SMT MRAM array with shunting transistors between bit lines	Yutaka Nakamura, John K. DeBrosse	2013-10-22	$5,163,000
8437181	Shared bit line SMT MRAM array with shunting transistors between the bit lines	Yutaka Nakamura, John K. DeBrosse	2013-05-07	$10,737,000
8274819	Read disturb free SMT MRAM reference cell circuit	—	2012-09-25
8248841	Boosted gate voltage programming for spin-torque MRAM array	—	2012-08-21
8018758	Gate drive voltage boost schemes for memory array	—	2011-09-13
7986572	Magnetic memory capable of minimizing gate voltage stress in unselected memory cells	—	2011-07-26
7977111	Devices using addressable magnetic tunnel junction array to detect magnetic particles	Xizeng Shi, Pokang Wang	2011-07-12
7957183	Single bit line SMT MRAM array architecture and the programming method	—	2011-06-07
7852662	Spin-torque MRAM: spin-RAM, array	Po-Kang Wang	2010-12-14
7782661	Boosted gate voltage programming for spin-torque MRAM array	—	2010-08-24
7613868	Method and system for optimizing the number of word line segments in a segmented MRAM array	Xizeng Shi, Po-Kang Wang, Bruce Yee Yang	2009-11-03
7609543	Method and implementation of stress test for MRAM	Lejan Pu, Perng-Fei Yuh, Po-Kang Wang	2009-10-27
7499314	Reference cell scheme for MRAM	Po-Kang Wang, Xizeng Shi	2009-03-03
7480172	Programming scheme for segmented word line MRAM array	Xizeng Shi, Po-Kang Wang	2009-01-20
7369430	Adaptive algorithm for MRAM manufacturing	Xi Shi, Po-Kang Wang, Bruce Yee Yang	2008-05-06
7362644	Configurable MRAM and method of configuration	Po-Kang Wang, Xizeng Shi	2008-04-22
7321519	Adaptive algorithm for MRAM manufacturing	Xi Shi, Po-Kang Wang, Bruce Yee Yang	2008-01-22
7321507	Reference cell scheme for MRAM	Po-Kang Wang, Xizeng Shi	2008-01-22

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Hsu Kai Yang — 33 Patents

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