Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9246475 | Dual-complementary integrating duty cycle detector with dead band noise rejection | Jon Allan Faue | 2016-01-26 |
| RE44726 | Data inversion register technique for integrated circuit memory testing | Michael C. Parris | 2014-01-21 |
| 8510641 | Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix | — | 2013-08-13 |
| 8281219 | Error correction code (ECC) circuit test mode | Michael C. Parris | 2012-10-02 |
| 8239740 | Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix | — | 2012-08-07 |
| 7962837 | Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix | — | 2011-06-14 |
| 7631233 | Data inversion register technique for integrated circuit memory testing | Michael C. Parris | 2009-12-08 |
| 7586355 | Low skew clock distribution tree | Michael C. Parris | 2009-09-08 |
| 7583142 | Low skew differential amplifier using tail voltage reference and tail feedback | — | 2009-09-01 |
| 7506100 | Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks | Douglas Butler, Michael C. Parris, Kim C. Hardee | 2009-03-17 |
| 7370140 | Enhanced DRAM with embedded registers | Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan | 2008-05-06 |
| 7110306 | Dual access DRAM | Michael C. Parris, Douglas Butler | 2006-09-19 |
| 7099234 | Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM | Michael C. Parris, Douglas Butler | 2006-08-29 |
| 7002874 | Dual word line mode for DRAMs | Michael C. Parris, Douglas Butler | 2006-02-21 |
| 6912168 | Non-contiguous masked refresh for an integrated circuit memory | Michael C. Parris, Douglas Butler, Kim C. Hardee | 2005-06-28 |
| 6788122 | Clock controlled power-down state | — | 2004-09-07 |
| 6732305 | Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry | Michael C. Parris | 2004-05-04 |
| 6728931 | Time data compression technique for high speed integrated circuit memory devices | Michael C. Parris | 2004-04-27 |
| 6667927 | Refresh initiated precharge technique for dynamic random access memory arrays using look-ahead refresh | — | 2003-12-23 |
| 6657461 | System and method for high speed integrated circuit device testing utilizing a lower speed test environment | Michael C. Parris | 2003-12-02 |
| 6643212 | Simultaneous function dynamic random access memory device technique | Michael C. Parris | 2003-11-04 |
| 6625078 | Look-ahead refresh for an integrated circuit memory | Kim C. Hardee | 2003-09-23 |
| 6622198 | Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture | — | 2003-09-16 |
| 6608797 | Automatic delay technique for early read and write operations in synchronous dynamic random access memories | Michael C. Parris, Kim C. Hardee | 2003-08-19 |
| 6347357 | Enhanced DRAM with embedded registers | Ronald H. Sartore, Kenneth J. Mobley, Donald G. Carrigan | 2002-02-12 |