Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9350338 | Linear progression delay register | Shane Pinit Yingtavorn | 2016-05-24 |
| 9252759 | Linear progression delay register | Shane Pinit Yingtavorn | 2016-02-02 |
| 9246475 | Dual-complementary integrating duty cycle detector with dead band noise rejection | Oscar Frederick Jones, Jr. | 2016-01-26 |
| 8594114 | Shielding of datalines with physical placement based on time staggered access | — | 2013-11-26 |
| 7889579 | Using differential data strobes in non-differential mode to enhance data capture window | — | 2011-02-15 |
| 7830734 | Asymetric data path position and delays technique enabling high speed access in integrated circuit memory devices | — | 2010-11-09 |
| 7764565 | Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks | — | 2010-07-27 |
| 7440351 | Wide window clock scheme for loading output FIFO registers | Van Butler | 2008-10-21 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM | Steve Eaton, Michael A. Murray | 2008-03-25 |
| 7298669 | Tri-mode clock generator to control memory array access | — | 2007-11-20 |
| 7251172 | Efficient register for additive latency in DDR2 mode of operation | Craig Barnett | 2007-07-31 |
| 7224637 | Tri-mode clock generator to control memory array access | — | 2007-05-29 |
| 7218564 | Dual equalization devices for long data line pairs | John D. Heightley | 2007-05-15 |
| 7167052 | Low voltage differential amplifier circuit for wide voltage range operation | John D. Heightley | 2007-01-23 |
| 7102439 | Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels | John D. Heightley | 2006-09-05 |
| 7091746 | Reduced device count level shifter with power savings | — | 2006-08-15 |
| 7061823 | Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices | Steve Eaton | 2006-06-13 |
| 7039822 | Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section | Harold Brett Meadows | 2006-05-02 |
| 7016235 | Data sorting in memories | Steve Eaton | 2006-03-21 |
| 6903592 | Limited variable width internal clock generation | — | 2005-06-07 |
| 6788589 | Programmable latch circuit inserted into write data path of an integrated circuit memory | — | 2004-09-07 |
| 6768367 | Pre-biased voltage level shifting circuit for integrated circuit devices utilizing differing power supply levels | Harold Brett Meadows | 2004-07-27 |
| 6741520 | Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices | — | 2004-05-25 |
| 6741488 | Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device | John D. Heightley | 2004-05-25 |
| 6621747 | Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices | — | 2003-09-16 |